-
2
-
-
0034852166
-
Analysis of non-uniform temperature-dependent interconnect performance in high performance ics
-
June
-
A. Ajami, K. Banerjee, M. Pedram, and L. van Ginneken. Analysis of non-uniform temperature-dependent interconnect performance in high performance ics. In 41st Design Automation Conference, pages 567-572, June 2001.
-
(2001)
41st Design Automation Conference
, pp. 567-572
-
-
Ajami, A.1
Banerjee, K.2
Pedram, M.3
Van Ginneken, L.4
-
6
-
-
0003465202
-
The simplescalar tool set, version 2.0
-
U. of Wisconsin, Madison, June
-
D. C. Burger and T. M. Austin. The simplescalar tool set, version 2.0. Technical Report CS-TR-97-1342, U. of Wisconsin, Madison, June 1997.
-
(1997)
Technical Report
, vol.CS-TR-97-1342
-
-
Burger, D.C.1
Austin, T.M.2
-
9
-
-
0007997616
-
Arb: A hardware mechanism for dynamic reordering of memory references
-
May
-
M. Franklin and G. S. Sohi. Arb: A hardware mechanism for dynamic reordering of memory references. IEEE Transactions on Computers, 46(5), May 1996.
-
(1996)
IEEE Transactions on Computers
, vol.46
, Issue.5
-
-
Franklin, M.1
Sohi, G.S.2
-
12
-
-
0009613335
-
The microarchitecture of the pentium 4 processor
-
G. Hinton, D. Sager, M. Upton, D. Boggs, D. Carmean, A. Kyker, and P. Roussel. The microarchitecture of the pentium 4 processor. Intel Technology Journal Q1, 2001.
-
(2001)
Intel Technology Journal Q1
-
-
Hinton, G.1
Sager, D.2
Upton, M.3
Boggs, D.4
Carmean, D.5
Kyker, A.6
Roussel, P.7
-
14
-
-
0038684860
-
Temperature-aware microarchitecture
-
June
-
K.Skadron, M.Stan, W. Huang, S.Velusamy, K. Sankaranarayanan, and D. Tarjan. Temperature-aware microarchitecture. In 30th Annual International Symposium on Computer Architecture, pages 2-13, June 2003.
-
(2003)
30th Annual International Symposium on Computer Architecture
, pp. 2-13
-
-
Skadron, K.1
Stan, M.2
Huang, W.3
Velusamy, S.4
Sankaranarayanan, K.5
Tarjan, D.6
-
18
-
-
33745166097
-
An evaluation of deeply decoupled cores
-
A. Shayesteh, E. Kursun, S. Sair, T. Sherwood, and G. Reinman. An evaluation of deeply decoupled cores. In University of California Los Angeles Tech Report CS-2004-09, 2004.
-
(2004)
University of California Los Angeles Tech Report
, vol.CS-2004-09
-
-
Shayesteh, A.1
Kursun, E.2
Sair, S.3
Sherwood, T.4
Reinman, G.5
-
21
-
-
0003450887
-
Cacti 3.0: An integrated cache timing, power, and area model
-
P. Shivakumar and Norman P. Jouppi. Cacti 3.0: An integrated cache timing, power, and area model. In Technical Report, 2001.
-
(2001)
Technical Report
-
-
Shivakumar, P.1
Jouppi, N.P.2
-
22
-
-
0035311434
-
Instruction-level distributed processing
-
April
-
J. E. Smith. Instruction-level distributed processing. IEEE Computer, 34(4):59-65, April 2001.
-
(2001)
IEEE Computer
, vol.34
, Issue.4
, pp. 59-65
-
-
Smith, J.E.1
-
25
-
-
0034462496
-
A framework for dynamic energy effiency and temperature management
-
December
-
W.Huang, J.Renau, S-M.Yoo, and J. Torrellas. A framework for dynamic energy effiency and temperature management. In 33rd International Symposium on Microarchitecture, pages 202-213, December 2000.
-
(2000)
33rd International Symposium on Microarchitecture
, pp. 202-213
-
-
Huang, W.1
Renau, J.2
Yoo, S.-M.3
Torrellas, J.4
-
27
-
-
34249306904
-
Hotleakage: A temperature-aware model of subthreshold and gate leakage for architects
-
March
-
Y. Zhang, D. Parikh, K. Sankaranarayanan, K. Skadron, and M. Stan. Hotleakage: A temperature-aware model of subthreshold and gate leakage for architects. In University of Virginia Dept of Computer Science Tech Report CS-2003-05, March 2003.
-
(2003)
University of Virginia Dept of Computer Science Tech Report
, vol.CS-2003-05
-
-
Zhang, Y.1
Parikh, D.2
Sankaranarayanan, K.3
Skadron, K.4
Stan, M.5
|