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Volumn 3471 LNCS, Issue , 2005, Pages 46-60

Low-overhead core swapping for thermal management

Author keywords

[No Author keywords available]

Indexed keywords

ACTIVITY MIGRATION; CORE SWAPPING; TEMPERATURE MANAGEMENT TECHNIQUES; THERMAL EFFICIENCY;

EID: 33745166655     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/11574859_4     Document Type: Conference Paper
Times cited : (6)

References (27)
  • 2
    • 0034852166 scopus 로고    scopus 로고
    • Analysis of non-uniform temperature-dependent interconnect performance in high performance ics
    • June
    • A. Ajami, K. Banerjee, M. Pedram, and L. van Ginneken. Analysis of non-uniform temperature-dependent interconnect performance in high performance ics. In 41st Design Automation Conference, pages 567-572, June 2001.
    • (2001) 41st Design Automation Conference , pp. 567-572
    • Ajami, A.1    Banerjee, K.2    Pedram, M.3    Van Ginneken, L.4
  • 6
    • 0003465202 scopus 로고    scopus 로고
    • The simplescalar tool set, version 2.0
    • U. of Wisconsin, Madison, June
    • D. C. Burger and T. M. Austin. The simplescalar tool set, version 2.0. Technical Report CS-TR-97-1342, U. of Wisconsin, Madison, June 1997.
    • (1997) Technical Report , vol.CS-TR-97-1342
    • Burger, D.C.1    Austin, T.M.2
  • 9
    • 0007997616 scopus 로고    scopus 로고
    • Arb: A hardware mechanism for dynamic reordering of memory references
    • May
    • M. Franklin and G. S. Sohi. Arb: A hardware mechanism for dynamic reordering of memory references. IEEE Transactions on Computers, 46(5), May 1996.
    • (1996) IEEE Transactions on Computers , vol.46 , Issue.5
    • Franklin, M.1    Sohi, G.S.2
  • 21
    • 0003450887 scopus 로고    scopus 로고
    • Cacti 3.0: An integrated cache timing, power, and area model
    • P. Shivakumar and Norman P. Jouppi. Cacti 3.0: An integrated cache timing, power, and area model. In Technical Report, 2001.
    • (2001) Technical Report
    • Shivakumar, P.1    Jouppi, N.P.2
  • 22
    • 0035311434 scopus 로고    scopus 로고
    • Instruction-level distributed processing
    • April
    • J. E. Smith. Instruction-level distributed processing. IEEE Computer, 34(4):59-65, April 2001.
    • (2001) IEEE Computer , vol.34 , Issue.4 , pp. 59-65
    • Smith, J.E.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.