A highly linear filter and VGA chain with novel DC-offset correction in 90nm digital CMOS process

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn 2005, Issue , 2005, Pages 302-303

  Elmala, Mostafa ^a   Carlton, Brent ^a   Bishop, Ralph ^a   Soumyanath, Krishnamurthy ^a  

^a INTEL RESEARCH   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC FILTERS; LOCAL AREA NETWORKS; OPTIMIZATION;

LINEAR FILTER; LOW VOLTAGE OPERATION; OFFSET CORRECTION; VGA CHAIN;

CMOS INTEGRATED CIRCUITS;

EID: 33745139860     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSIC.2005.1469391     Document Type: Conference Paper

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