Synchronization-at-retirement for pipeline verification

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 3312, Issue , 2004, Pages 113-127

  Aagaard, Mark D ^a   Day, Nancy A ^a   Jones, Robert B ^b  

^a UNIVERSITY OF WATERLOO   (Canada)

^b INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER AIDED DESIGN; FORMAL METHODS; SYNCHRONIZATION;

BRANCH PREDICTION; EXPERIMENTAL EVIDENCE; MEMORY OPERATIONS; PIPELINED PROCESSOR; PROOF OBLIGATIONS; REDUCED COMPLEXITY; VERIFICATION COMPLEXITY;

PIPELINES;

EID: 33745123504     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/978-3-540-30494-4_9     Document Type: Article

References (17)

1. [ACDJ03] M. D. Aagaard, B. Cook, N. A. Day, and R. B. Jones. A framework for super-scalar microprocessor correctness statements. Software Tools for Technology Transfer, 4(3):298-312, 2003.
2. [ADJ04] M. D. Aagaard, N. A. Day, and R. B. Jones. Equivalence of sync-at-fetch and sync-at-retire correctness for pipeline circuits. Technical Report CS2004-31, University of Waterloo, School of Computer Science, September 2004.
3. [AP98] T. Arons and A. Pnueli. Verifying Tomasulo's algorithm by refinement. Technical report, Dept. of Computer Science, Weizmann Institute, October 1998.
4. [AP00] T. Arons and A. Pnueli. A comparison of two verification methods for speculative instruction execution with exceptions. In TACAS, vol 1785 of LNCS, pp 487-502. Springer, 2000.
5. [AS99] Arvind and X. Shen. Using term rewriting systems to design and verify processors. IEEE Micro, 19(3):36-46, 1999.
6. [BB04] C. Barrett and S. Berezin. CVC Lite: A new implementation of the cooperating validity checker. In CAV, vol 3114 of LNCS, pp 515-518. Springer, 2004.
7. [BD94] J. Burch and D. Dill. Automatic verification of pipelined microprocessor control. In D. L. Dill, editor, CAV, vol 818 of LNCS, pp 68-80. Springer, 1994.
8. [BDL96] C. Barrett, D. Dill, and J. Levitt. Validity checking for combinations of theories with equality. In FMCAD, vol 1166 of LNCS, pp 187-201. Springer, 1996.
9. [FH96] A. Fox and N. Harman. Algebraic models of correctness for microprocessors. In FMCAD, vol 1166 of LNCS, pp 346-361. Springer, 1996.
10. [FH03] A. Fox and N. Harman. Algebraic models of correctness for abstract pipelines. The Journal of Algebraic and Logic Programming, 57:71-107, 2003.
11. [HGS03] R. Hosabettu, G. Gopalakrishnan, and M. K. Srivas. Formal verification of a complex pipelined processor. Formal Methods in System Design, 23(2):171-213, September 2003.
12. [JM01] R. Jhala and K. L. McMillan. Microarchitecture verification by compositional model checking. In CAV, vol 2102 of LNCS, pp 396-410. Springer, 2001.
13. [LSB02] S. K. Lahiri, S. A. Seshia, and R. E. Bryant. Modeling and verification of out-of-order microprocessors in UCLID. In FMCAD, vol 2517 of LNCS, pp 142-158. Springer, 2002.
14. [Mic] http://www.cs.uwaterloo.ca/~nday/microbox.
15. [Mil71] R. Milner. An algebraic definition of simulation between programs. In Joint Conf. on AI, pp 481-489. British Computer Society, 1971.
16. [MS04] P. Manolios and S. K. Srinivasan. Automatic verification of safety and liveness for Xscale-like processor models using web refinements. In DATE, pp 168-175, 2004.
17. [PA98] A. Pnueli and T. Arons. Verification of data-insensitive circuits: An in-order-retirement case study. In FMCAD, vol 1522 of LNCS, pp 351-368. Springer, 1998.