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Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 3824 LNCS, Issue , 2005, Pages 311-320

Hierarchical Graph: A new cost effective architecture for network on chip

(3) Vahdatpour, Alireza a Tavakoli, Ahmadreza a Falaki, Mohammad Hossein a

a SHARIF UNIVERSITY OF TECHNOLOGY (Iran)

Author keywords

[No Author keywords available]

Indexed keywords

APPLICATION SPECIFIED CHIPS; HIERARCHICAL GRAPH; IMPLEMENTATION PROCESS; NETWORK ON CHIP (NOC);

BENCHMARKING; COMPUTER NETWORKS; HIERARCHICAL SYSTEMS; TELECOMMUNICATION TRAFFIC; TOPOLOGY;

MICROPROCESSOR CHIPS;

EID: 33744951837 PISSN: 03029743 EISSN: 16113349 Source Type: Book Series
DOI: 10.1007/11596356_33 Document Type: Conference Paper

Times cited : (9)

References (9)

1
- 84858903144
- ITRS. International technology roadmap for semiconductors - 2004 edition, http://public.itrs.net/
- ITRS. International Technology Roadmap for Semiconductors - 2004 Edition

2
- 0036149420
- Networks on chip: A new SoC paradigm
- January
- L. Benini and G. De Micheli, Networks on Chip: A New SoC paradigm, IEEE Computer, January 2002(Vol. 35, No. 1), pp. 70-78.
- (2002) IEEE Computer , vol.35 , Issue.1 , pp. 70-78
- Benini, L.¹ De Micheli, G.²

3
- 0020951903
- The OSI reference model
- December
- JD Day, H Zimmermann, "The OSI reference model", Proceedings IEEE, 1334-1340, December 1983.
- (1983) Proceedings IEEE , pp. 1334-1340
- Day, J.D.¹ Zimmermann, H.²

4
- 84948696213
- A network on chip architecture and design methodology
- Pittsburgh, Pennsylvania, USA, April
- Shashi Kumar, et al., "A Network on Chip Architecture and Design Methodology", IEEE Computer Society Annual Symposium on VLSI, Pittsburgh, Pennsylvania, USA, April 2002.
- (2002) IEEE Computer Society Annual Symposium on VLSI
- Kumar, S.¹

5
- 33645853882
- Simulation and evaluation for a network on chip architecture using Ns-2
- Copenhagen, November
- Yi-Ran Sun, Shashi Kumar, Axel Jantsch, "Simulation and Evaluation for a Network on Chip Architecture Using Ns-2", Proceedings of 20th NORCHIP conference, Copenhagen, November 2002.
- (2002) Proceedings of 20th NORCHIP Conference
- Sun, Y.-R.¹ Kumar, S.² Jantsch, A.³

6
- 33744962492
- Vu-Duc Ngo and Hae-Wook Choi "On Chip Network: Topology design and evaluation using NS2".
- On Chip Network: Topology Design and Evaluation Using NS2
- Ngo, V.-D.¹ Choi, H.-W.²

7
- 10444269476
- Network on chip simulations for benchmarking
- Banff, Canada, July
- Daniel Wiklund, Sumant Sathe, and Dake Liu, "Network on chip simulations for benchmarking", Proceedings of the International workshop on SoC for real-time applications, Banff, Canada, July 2004.
- (2004) Proceedings of the International Workshop on SoC for Real-time Applications
- Wiklund, D.¹ Sathe, S.² Liu, D.³

8
- 14844319294
- A virtual channel router for on-chip networks
- Santa ClaraSep, California
- Nikolay Kavaldjiev, Gerard J. M. Smit, Pierre G. Jansen "A Virtual Channel Router for On-chip Networks", Proceedings of IEEE International SOC Conference, Santa ClaraSep, California, 2004
- (2004) Proceedings of IEEE International SOC Conference
- Kavaldjiev, N.¹ Smit, G.J.M.² Jansen, P.G.³

9
- 26644463857
- The network simulator - NS-2, http://www.isi.edu/nsnam/ns/
- The Network Simulator - NS-2

* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.