SCOPUS 정보 검색 플랫폼

Volumn 24, Issue 3, 2006, Pages 1341-1343

Interface configuration and Fermi-level pinning of fully silicided gate and high-K dielectric stack

Author keywords

[No Author keywords available]

Indexed keywords

DIELECTRIC MATERIALS; FERMI LEVEL; INTERFACES (MATERIALS); POLYSILICON;

FERMI-LEVEL PINNING; FULLY SILICIDED (FUSI); METAL-INDUCED GAP STATES (MIGS);

GATES (TRANSISTOR);

EID: 33744827698 PISSN: 10711023 EISSN: None Source Type: Journal
DOI: 10.1116/1.2198849 Document Type: Article

Times cited : (4)

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