Optimization of substrate doping for back-gate control in SOI T-RAM memory technology

Proceedings - IEEE International SOI Conference

Volumn 2005, Issue , 2005, Pages 215-216

  Ershov, M ^a   Nemati, F ^a   Gupta, R ^a   Gopalakrishnan, V ^a   Gooty, R ^a   Tarabbia, M ^a   Yang, K J ^a   Banna, S ^a   Hayes, D ^a   Cho, H J ^a   Robins, S ^a  

^a T RAM Inc   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

GATES (TRANSISTOR); OPTIMIZATION; RANDOM ACCESS STORAGE; SILICON ON INSULATOR TECHNOLOGY; SUBSTRATES;

BACK GATE CONTROL; GATE CONTROL; TRANSIENT PROBLEM;

DATA STORAGE EQUIPMENT;

EID: 33744758910     PISSN: 1078621X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/SOI.2005.1563593     Document Type: Conference Paper

References (1)

1. F.Nemati et al., IEDM Tech. Digest, p.273, 2004.