A low-power entropy-coding analog/digital converter with integrated data compression

European Solid-State Circuits Conference

Volumn , Issue , 2003, Pages 173-176

  Peck, R ^a   Schroeder, D ^a  

^a HAMBURG UNIVERSITY OF TECHNOLOGY   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

CIRCUIT ARCHITECTURES; CMOS PROCESSS; LOW POWER; LOW-POWER OPERATION; POWER SAVINGS; SINGLE PROCESS;

CMOS INTEGRATED CIRCUITS; ENTROPY;

DATA COMPRESSION;

EID: 33744488727     PISSN: 19308833     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ESSCIRC.2003.1257100     Document Type: Conference Paper

References (8)

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2. A. Gersho, R. M. Gray; Vector Quantization and Signal Compression. Kluwer Academic Publishers, 1992
3. J. L. McCreary, P. R. Gray; "All-MOS charge redistribution analog-to-digital conversion techniques- Part I". IEEE J. Solid-state Circuits, vol. 10 (1975), no. 6, p. 371
4. K. Satou, K. Tsuji, M. Sahoda, H. Otsuka, K. Mori, T. Iida; "A 12 bit 1 MHz ADC with 1 mW power consumption". Custom Integrated Circuits Conference (CICC'94), 1.-4. Mai 1994, p. 515
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6. B. Razavi; Principles of Data Conversion System Design. IEEE Press, 1995
7. F. Goodenough;, ADCs Move to Cut Power Dissipation". Electronic Design, January 9 (1995), p. 69
8. T. M. Cover, J. A. Thomas; Elements of Information Theory. John Wiley &Sons, 1991.