Detecting stuck-open faults with stuck-at test sets

Proceedings of the Custom Integrated Circuits Conference

Volumn , Issue , 1989, Pages

  Millman, Steven D ^a   McCluskey, Edward J ^a  

^a STANFORD UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

STUCK-OPEN FAULTS; TEST LENGTHS; TEST SETS;

INTEGRATED CIRCUITS;

EID: 33744479053     PISSN: 08865930     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/CICC.1989.56809     Document Type: Conference Paper

References (7)

1. Brglez, F., and H. Fujiwara, "A Neutral Netlist of 10 Combinational Benchmark Circuits and a Target Translator in FORTRAN," distributed at the 1985 IEEE International Symposium on Circuits and Systems, Kyoto, Japan, June 5-7, 1985.
2. Chandramouli, R.,"On Testing Stuck-Open Faults," Proc. FTCS 13, Milano, Italy, June 28-30, 1983, pp. 258-265.
3. Cox, H., and J. Rajski, "Stuck-Open and Transitions Fault Testing in CMOS Complex Gates," Proc. Int. Test Conf., Washington, D.C., Sept.12-14, 1988, pp. 688-694.
4. Koeppe, S., "Optimal Layout to Avoid CMOS Stuck-Open Faults," Proc. 24th DAC, Miami Beach, FL, June 28 - July 1, 1987, pp. 829-835.
5. Millman, S., E.J. McCluskey.'Detecting Bridging Faults with Stuck-at Test Sets," Proc. Int. Test Conf., Washington, D.C., Sept.12-14, 1988, pp. 773-783.
6. Reddy, S.M., and M.K. Reddy, "Testable Realizations for FET Stuck-Open Faults in CMOS Combinational Logic Circuits," IEEE Trans. Comput., Vol. C-35, No. 8, Aug. 1986, pp. 742-754.
7. Wadsack, R.L., "Fault Modeling and Logic Simulation of CMOS and MOS Integrated Circuits," Bell System Tech. J., Vol. 57, No. 5, May-June 1978, pp. 1449-1474.