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Volumn II, Issue , 2005, Pages 970-975

Buffer insertion considering process variation

Author keywords

[No Author keywords available]

Indexed keywords

BUFFER INSERTION ALGORITHMS; PROCESS VARIATIONS; RECURSIVE ALGORITHMS; TIMING ANALYSIS;

EID: 33646931776     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.2005.85     Document Type: Conference Paper
Times cited : (14)

References (10)
  • 2
    • 33748598084 scopus 로고    scopus 로고
    • Impact of die-to-die and within-die parameter fluctuations on the maximum clock frequency distribution
    • Feb
    • K. A. Bowman, S. G. Duvall, and J. D. Meindl, ''Impact of die-to-die and within-die parameter fluctuations on the maximum clock frequency distribution," in ISSCC 01, Feb 2001.
    • (2001) ISSCC 01
    • Bowman, K.A.1    Duvall, S.G.2    Meindl, J.D.3
  • 3
    • 0042635808 scopus 로고    scopus 로고
    • Death, taxes and failing chips
    • Jun
    • C. Visweswariah, "Death, taxes and failing chips." in DAC 03, Jun 2003.
    • (2003) DAC 03
    • Visweswariah, C.1
  • 4
    • 0041633575 scopus 로고    scopus 로고
    • Statistical timing for parametric yield prediction of digital integrated circuits
    • Jun
    • J. Jess, K. Kalafala, S. Naidu, R. Otten, and C. Visweswariah, "Statistical timing for parametric yield prediction of digital integrated circuits," in DAC 03, Jun 2003.
    • (2003) DAC 03
    • Jess, J.1    Kalafala, K.2    Naidu, S.3    Otten, R.4    Visweswariah, C.5
  • 5
    • 0041633857 scopus 로고    scopus 로고
    • Computation and refinement of statistical bounds on circuit delay
    • Jun
    • A. Agarwal, D. Blaauw, V. Zolotov, and S. Vradhula, "Computation and refinement of statistical bounds on circuit delay," in DAC 03, Jun 2003.
    • (2003) DAC 03
    • Agarwal, A.1    Blaauw, D.2    Zolotov, V.3    Vradhula, S.4
  • 6
    • 0025594311 scopus 로고
    • Buffer placement in distributed RC-tree networks for minimal Elmore delay
    • L. P. P. P. van Ginneken, "Buffer placement in distributed RC-tree networks for minimal Elmore delay." in Proc. IEEE Int. Symp. on Circuits and Systems, pp. 865-868, 1990.
    • (1990) Proc. IEEE Int. Symp. on Circuits and Systems , pp. 865-868
    • Van Ginneken, L.P.P.P.1
  • 7
    • 0030697661 scopus 로고    scopus 로고
    • Wire segmenting for improved buffer insertion
    • Jun
    • C. J. Alpert and A. Devgan, "Wire segmenting for improved buffer insertion," in DAC 97, Jun 1997. 588-593.
    • (1997) DAC 97 , pp. 588-593
    • Alpert, C.J.1    Devgan, A.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.