Power-performance trade-offs in nanometer-scale multi-level caches considering total leakage

Proceedings -Design, Automation and Test in Europe, DATE '05

Volumn I, Issue , 2005, Pages 650-651

  Bai, Robert ^a   Kim, Nam Sung ^b   Kgil, Tae Ho ^a   Sylvester, Dennis ^a   Mudge, Trevor ^a  

^a University of Michigan   (United States)

^b INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CACHE SYSTEMS; DYNAMIC POWER; NANOMETER SCALE; POWER-PERFORMANCE;

CACHE MEMORY; COSTS; LEAKAGE CURRENTS; OPTIMIZATION; PRODUCT DESIGN;

CHIP SCALE PACKAGES;

EID: 33646925656     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.2005.243     Document Type: Conference Paper

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