A time slice based scheduler model for system level design

Proceedings -Design, Automation and Test in Europe, DATE '05

Volumn I, Issue , 2005, Pages 378-383

  Lavagno, Luciano ^a   Passerone, Claudio ^a   Shah, Vishal ^a   Watanabe, Yosinori ^b  

^a POLITECNICO DI TORINO   (Italy)

^b CADENCE DESIGN SYSTEMS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER HARDWARE; COMPUTER SOFTWARE; MATHEMATICAL MODELS; MULTITASKING; OPTIMAL SYSTEMS; SCHEDULING; TIME SHARING SYSTEMS;

FUNCTIONALITY; HARD WARE/SOFTWARE DESIGN; TASK SCHEDULERS; UPGRADABILITY;

EMBEDDED SYSTEMS;

EID: 33646922611     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.2005.41     Document Type: Conference Paper

References (11)

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