-
6
-
-
19344363853
-
-
Arne Hamann, Rafik Henia, Marek Jersak, Razvan Racu, Kai Richter, and Rolf Ernst. SymTA/S - Symbolic Timing Analysis for Systems, http://www.symta. org/.
-
SymTA/S - Symbolic Timing Analysis for Systems
-
-
Hamann, A.1
Henia, R.2
Jersak, M.3
Racu, R.4
Richter, K.5
Ernst, R.6
-
7
-
-
2442513349
-
Rate analysis for streaming applications with on-chip buffer constraints
-
Yokohama, Japan, January
-
A. Maxiaguine, S. Künzli, S. Chakraborty, and L. Thiele. Rate analysis for streaming applications with on-chip buffer constraints. In Proc. Asia and South Pacific Design Automation Conference (ASP-DAC), pages 131-136, Yokohama, Japan, January 2004.
-
(2004)
Proc. Asia and South Pacific Design Automation Conference (ASP-DAC)
, pp. 131-136
-
-
Maxiaguine, A.1
Künzli, S.2
Chakraborty, S.3
Thiele, L.4
-
8
-
-
0013037475
-
Exploring embedded-systems architectures with artemis
-
November
-
A.D. Pimentel, P. Lieverse, P. van der Wolf, L.O. Hertzberger, and E.F. Deprettere, Exploring embedded-systems architectures with Artemis. In IEEE Computer, November 2001.
-
(2001)
IEEE Computer
-
-
Pimentel, A.D.1
Lieverse, P.2
Van Der Wolf, P.3
Hertzberger, L.O.4
Deprettere, E.F.5
-
9
-
-
3042608105
-
Design optimization of multi-cluster embedded systems for real-time applications
-
Paris, France
-
Paul Pop, Petru Eles, Zebo Peng, Viacheslav Izosimov, Magnus Hellring, and Olof Bridal. Design optimization of multi-cluster embedded systems for real-time applications. In Proc. of Design, Automation and Test in Europe (DATE'04), Paris, France, 2004.
-
(2004)
Proc. of Design, Automation and Test in Europe (DATE'04)
-
-
Pop, P.1
Eles, P.2
Peng, Z.3
Izosimov, V.4
Hellring, M.5
Bridal, O.6
-
10
-
-
21644480237
-
Automated design space exploration for embedded computer systems
-
Hewlett-Packard Laboratories
-
G. Snider. Automated design space exploration for embedded computer systems. Technical Report HPL-2001-220, Hewlett-Packard Laboratories, 2001.
-
(2001)
Technical Report
, vol.HPL-2001-220
-
-
Snider, G.1
-
11
-
-
0036044485
-
A framework for evaluating design tradeoffs in packet processing architectures
-
New Orleans, USA, ACM Press
-
L. Thiele, S. Chakraborty, M. Gries, and S. Künzli, A framework for evaluating design tradeoffs in packet processing architectures. In Proc. 39th Design Automation Conference (DAC), pages 880-885, New Orleans, USA, 2002. ACM Press.
-
(2002)
Proc. 39th Design Automation Conference (DAC)
, pp. 880-885
-
-
Thiele, L.1
Chakraborty, S.2
Gries, M.3
Künzli, S.4
-
12
-
-
0004140075
-
SPEA2: Improving the strength pareto evolutionary algorithm
-
Gloriastrasse 35, CH-8092 Zurich, Switzerland
-
Eckart Zitzler, Marco Laumanns, and Lothar Thiele. SPEA2: Improving the Strength Pareto Evolutionary Algorithm. Technical Report 103, Gloriastrasse 35, CH-8092 Zurich, Switzerland, 2001.
-
(2001)
Technical Report
, vol.103
-
-
Zitzler, E.1
Laumanns, M.2
Thiele, L.3
|