A methodology for automated verification of synthesized RTL designs and its integration with a high-level synthesis tool

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 1522, Issue , 1998, Pages 102-204

  Mansouri, Nazanin ^a   Vemuri, Ranga ^a  

^a 705 Engineering Research Center   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTER AIDED DESIGN; DESIGN; FORMAL LOGIC; FORMAL METHODS; FORMAL SPECIFICATION; FUNCTIONS; MATHEMATICAL OPERATORS; SPECIFICATIONS; SYNTHESIS (CHEMICAL);

AUTOMATED VERIFICATION; BEHAVIORAL SPECIFICATION; CORRECTNESS CONDITIONS; HIGHER ORDER LOGIC; HUMAN INTERACTIONS; MATHEMATICAL PROPERTIES; UNINTERPRETED FUNCTION SYMBOLS; VERIFICATION METHODOLOGY;

HIGH LEVEL SYNTHESIS;

EID: 33646868475     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: None     Document Type: Conference Paper

References (31)

1. G. De Micheli, “Synthesis and Optimization of Digital Circuits”, McGraw-Hill, 1994.
2. D.E. Thomas et al., “Algorithmic and Register Transfer Level Synthesis: The System Architect’s Workbench”, Kluwer Academic Publishers, 1990.
3. Srinivas Devadas, Hi-Keung Tony Ma, Richard Newton, ”On Verification of Sequential Machines at Differing Levels of Abstraction”, IEEE Transactions on Computer-Aided Design, June 1988.
4. Michael McFarland, “An Abstract Model of Behavior for Hardware Descriptions”, IEEE Transactions on Computers, July 1983.
5. F. Corella, R. Camposano, R. Bergamaschi, M. Payer, “Verification of Synchronous Sequential Circuits Obtained from Algorithmic Specifications,” Proc. Intl. Work­shop on Formal Methods in VLSI Design, Miami, 1991.
6. Reinaldo A. Bergamaschi, Salil Raje, ’’Observable Time Windows: Verifying The Results of High-Level Synthesis”, IEEE Design & Test of Computers”, May 1997.
7. Steven Johnson, “Synthesis of Digital Designs from Recursion Equations”, MIT Press, Cambridge, 1984.
8. Ranga Vemuri, “On the Notion of Normal Form Register-Level Structures and Its Applications in Design-Space Exploration ”, European Design Automation Conference, March 1990.
9. F. Feldbusch, R. Kumar, “Verification of Synthesized Circuits at Register Transfer Level with Flow Graphs,” Proc. IEEE EDAC Conf., pp. 22-26, 1991.
10. Sreeranga Rajan, “Correctness Transformations in High Level Synthesis: Formal Verification”, Proceedings of the International Conference on Computer Hardware Description Languages, Japan, August 1995.
11. N. Shankar, S. Owre and J. M. Rushby, ”The PVS Proof Checker: A Reference Manual (Beta Release)”, March 1993.
12. Dirk Eisnbiegler, Ramayya Kumar, “Formally Embedding Existing High Level Synthesis Algorithms”, “Correct Hardware Design and Verification Methods”, Germany, October 1995.
13. Luc Claesen, Mark Genoe, Eric Verlind, Frank Proesmans, Hugo De Man, “SFG- Tracing: A Methodology of Design for Verifiability”, Proceedings of Advanced Workshop on Correct Hardware Design Methodologies, North-Holland, 1991.
14. Luc Claesen, Frank Proesmans, Eric Verlind, Hugo De Man, “SFG-Tracing: A Methodology for the Automatic Verification of MOS Transistor Level Implementations from High-Level Behavioral Specifications”, Proc. Intl. Workshop on Formal Methods in VLSI Design, Miami, 1991.
15. Francisco Corella, “Automated High-Level Verification Against Clocked Algorithmic Specifications,” Proc. Computer Hardware Description Languages and Their Applications, April 1993.
16. Francisco Corella, “Automated Verification of Behavioral Equivalence for Microprocessors”, Research Report, IBM Research division, T.J. Watson Research Center, 1992.
17. Jerry R. Burch and David L. Dill, “Automatic Verification of Pipelined Microprocessor Control”, Proceedings of Computer-Aided Verification, July 1994.
18. M. K. Srivas and S. P. Miller, “Formal Verification of the AAMP5 Microprocessor,” Chapter 7 in Industrial Applications of Formal Verification.
19. A. Takach and W. Wolf, “Scheduling Constraint Generation for Communicating Processes”, Princeton University, November 1993.
20. D. E. Thomas, R. L. Blackburn, and J. V. Rajan, “Linking the Behavioral and Structural Domains of Representation for Digital System Design”, IEEE Trans. CAD, vol. CAD-6, pp. 103-110, January 1987.
21. F. J. Kurdahi, A. C. Parker, “REAL: A Program for REgister ALlocation”, Proceedings of the 24th ACM/IEEE Design Automation Conference, pp. 210-215, 1987.
22. S. Owre, N. Shankar, J. M. Rushby, “The PVS Specification Language (Beta Release)”, June 1993.
23. J. Roy, N. Kumar, R. Dutta, R. Vemuri, “DSS: A Distributed High-Level Synthesis System”, IEEE Design and Test of Computers, June 1992.
24. R. Dutta, J. Roy, R. Vemuri, “Distributed Design Space Exploration for High-Level Synthesis Systems”, 29th Design Automation Conference, pp. 644-650, 1992.
25. Sriram Govindarajan, Ranga Vemuri, “Dynamic Bounding of Successor Force Computations in the Force Directed List Scheduling Algorithm”, International Conference on Computer Design (ICCD), October 1997.
26. Sriram Govindarajan, Ranga Vemuri, Cone-Based Clustering Heuristic for List Scheduling Algorithms, Proceedings of the European Design and Test Conference, pp. 456-462., (ED&TC), March 1997.
27. Srinivas Katkoori, Jay Roy, Ranga Vemuri, “A Hierarchical Register Optimization Algorithm for Behavioral Synthesis”, Proceedings of International Conference on VLSI Design, pp. 126-134, Banglore, India 1996.
28. R. Vemuri et al, “Experiences in Functional Validation of a High Level Synthesis System”, 30th ACM/IEEE Design Automation Conference, 1993.
29. E.M. Clarke, E.A. Emerson, A.P. Sistla, “Automatic Verification of Finite-State Concurrent Systems using Temporal Logic Specifications”, ACM Trans. Prog. Lang. Syst., pp. 244-263, 1986.
30. N. Narasimhan, R. Vemuri, “Specification of Control Flow Properties for Verification of Synthesized VHDL Designs”, ’’Proceedings of Formal Methods in CAD”, pp. 327-345, Springer-Verlag, November 1996.
31. Kenneth L. McMillan, “Symbolic Model Checking: An Approach to the State Explosion Problem” Carnegie Mellon University, 1992