A programmable hardware path profiler

Proceedings of the 2005 International Symposium on Code Generation and Optimization, CGO 2005

Volumn 2005, Issue , 2005, Pages 217-228

  Vaswani, Kapil ^a   Thazhuthaveetil, Matthew J ^a   Srikant, Y N ^a  

^a INDIAN INSTITUTE OF SCIENCE   (India)

Author keywords

[No Author keywords available]

Indexed keywords

PATH PROFILER; PROGRAM OPTIMIZATIONS;

COMPUTER ARCHITECTURE; COMPUTER PROGRAMMING; FORMAL LOGIC; HIERARCHICAL SYSTEMS; INFORMATION ANALYSIS; MICROPROCESSOR CHIPS;

COMPUTER HARDWARE;

EID: 33646850554     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/CGO.2005.3     Document Type: Conference Paper

References (31)

1. G. Ammons, T. Ball, and J. R. Larus. Exploiting Hardware Performance Counters with Context Sensitive Profiling. In Proceedings of the SIGPLAN Conference on Programming Languages Design and Implementation, pages 85-96, 1997.
2. G. Ammons and J. R. Larus. Improving Data-flow Analysis with Path Profiles. In Proceedings of the SIGPLAN Conference on Programming Language Design and Implementation, pages 72-84, 1998.
3. M. Arnold and B. Ryder. A Framework for Reducing the cost of Instrumented Code. In Proceedings of the ACM SIGPLAN Conference on Programming Languages Design and Implementation, pages 168-179, June 2001.
4. T. Ball and J. R. Larus. Optimally Profiling and Tracing Programs. ACM Transactions on Programming Languages and Systems, pages 16(4):1319-1360, July 1994.
5. T. Ball and J. R. Larus. Efficient Path Profiling. In Proceedings of the 29th Annual International Symposium on Microarchitecture, pages 46-57, 1996.
6. D. Brooks, V. Tiwari, and M. Martonosi. Wattch: A Framework for Architectural-Level Power Analysis and Optimizations. In Proceedings of the Annual International Symposium on Computer Architecture, pages 83-94, 2000.
7. D. Burger, T. M. Austin, and S. Bennett. Evaluating Future Microprocessors: The SimpleScalar Toolset. Technical Report CS-TR-96-1308, University of Wisconsin-Madison, 1996.
8. T. M. Conte, B. Patel, K. N. Menezes, and J. S. Cox. Hardware-Based Profiling: An Effective Technique for Profile-Driven Optimization. International Journal of Parallel Programming, pages 187-206, Vol 24, No. 2, April 1996.
9. J. Dean, J. E. Hicks, C. A. Waldspurger, W. E. Weihl, and G. Chrysos. ProfileMe: Hardware Support for Instruction-Level Profiling on Out-of-Order Processors. In Proceedings of the Annual International Symposium on Microarchitecture, pages 292-302, December 1997.
10. P. T. Fellar. Value Profiling for Instructions and Memory Locations. CS98-581, University of California, San Diego, April 1998.
11. R. Gupta, D. A. Berson, and J. Z. Fang. Path Profile Guided Partial Redundancy Elimination Using Speculation. In Proceedings of the 1998 International Conference on Computer Languages, page 230, 1998.
12. W. W. Hwu and S. A. Mahlke. The Superblock: An Effective Technique for VLIW and Superscalar Compilation. The Journal of Supercomputing, pages 7(1-2):229-248, May 1993.
13. Q. Jacobson, E. Rotenberg, and J. E. Smith, Path-Based Next Trace Prediction. In Proceedings of the International Symposium on Microarchitecture, pages 14-23, 1997.
14. R. Joshi, M. D. Bond, and C. B. Zilles. Targeted Path Profiling: Lower Overhead Path Profiling for Staged Dynamic Optimization Systems. In Proceedings of the International Symposium on Code Generation and Optimization (CGO), pages 239-250, March 2004.
15. I. Kadayif, T. Chinoda, M. Kandemir, N. Vijaykrishnan, M. J. Irwin, and A. Sivasubramaniam. vEC: Virtual Energy Counters. In Proceedings of Workshop on Program Analysis for Software Tools and Engineering, pages 28-31, 2001.
16. M. B. Kamble and K. Ghose. Analytical Energy Dissipation Models for Low Power Caches. In Proceedings of the International Symposium on Low Power Electronics and Design, 1997.
17. A. KleinOsowski and D. J. Lilja. MinneSPEC: A New SPEC Benchmark Workload for Simulation-Based Computer Architecture Research. Computer Architecture Letters, 2002.
18. J. R. Larus. Whole Program Paths. In Proceedings of the ACM SIGPLAN Conference on Programming Language Design and Implementation, pages 259-269, 1999.
19. M. C. Merten, A. R. Trick, C. N. George, J. C. Gyllenhaal, and W. mei W. Hwu. A Hardware-Driven Profiling Scheme for Identifying Program Hot Spots to Support Runtime Optimization. In Proceedings of the 26th International Symposium on Computer Architecture, pages 136-147, June 1999.
20. R. Nair. Dynamic path-based branch correlation. In Proceedings of the Annual International Symposium on Microarchitecture, pages 15-23, 1995.
21. S. J. Patel and S. S. Lumetta. rePLay: A Hardware Framework for Dynamic Optimization. IEEE Transactions on Computers, June 2001.
22. R. Plackett and J. Burman. The Design of Optimal Multifactorial Experiments. Biometrika, Vol 33, Issue 4:305-325, June 1956.
23. E. Rotenberg, S. Bennett, and J. Smith. Trace Cache: a Low Latency Approach to High Bandwidth Instruction Fetching. In Proceedings of the 28th International Symposium on Microarchitecture, 1996.
24. B. Sprunt. Pentium 4 Performance Monitoring Features. IEEE Micro, pages 22(4):72-82, July-August 2002.
25. Sun Microsystems Inc. UltraSPARC User's Manual, 1997.
26. S. Tallam, X. Zhang, and R. Gupta. Extending Path Profiling across Loop Backedges and Procedure Boundaries. In Proceedings of the International Symposium on Code Generation and Optimization (CGO), pages 251-262. March 2004.
27. K. Vaswani, M. J. Thazhuthaveetil, and Y. N. Srikant. Representing, Detecting and Profiling Paths in Hardware. Technical Report IISc-CSA-TR-2004-7, Indian Institute of Science, May 2004.
28. T. Yasue, T. Suganuma, H. Komatsu, and T. Nakatani. Structural Path Profiling: An Efficient Online Path Profiling Framework for Just-In-Time Compilers. In International Conference on Parallel Architectures and Compilation Techniques (PACT), Sept-Oct 2003.
29. J. Yi, D. Lilja, and D. Hawkins. A Statistically Rigorous Approach for Improving Simulation Methodology. In Proceedings of the International Symposium on High Performance Computer Architecture, February 2003.
30. C. Young. Path-based Compilation. PhD thesis. Harvard University. Jan 1998.
31. C. Young and M. D. Smith. Better Global Scheduling Using Path Profiles. In Proceedings of the 30th International Symposium on Microarchitecture. November 1998.