On the single processor performance of simple lattice Boltzmann kernels

Computers and Fluids

Volumn 35, Issue 8-9, 2006, Pages 910-919

  Wellein, G ^a   Zeiser, T ^a   Hager, G ^a   Donath, S ^a  

^a UNIVERSITY OF ERLANGEN NUREMBERG   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER AIDED DESIGN; MICROPROCESSOR CHIPS; NUMERICAL METHODS; OPTIMIZATION; VECTORS;

CACHE-BLOCKING TECHNIQUES; DATA LAYOUTS; LATTICE BOLTZMANN KERNELS; SINGLE PROCESSOR PERFORMANCE;

COMPUTER ARCHITECTURE;

COMPUTER AIDED DESIGN; COMPUTER ARCHITECTURE; MICROPROCESSOR CHIPS; NUMERICAL METHODS; OPTIMIZATION; VECTORS;

EID: 33646809359     PISSN: 00457930     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.compfluid.2005.02.008     Document Type: Article

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