A problem reduction approach for scheduling semiconductor wafer fabrication facilities

IEEE Transactions on Semiconductor Manufacturing

Volumn 19, Issue 2, 2006, Pages 216-225

  Upasani, Abhijit A ^a   Uzsoy, Reha ^a,b,c   Sourirajan, Karthik ^a  

^a SCHOOL OF INDUSTRIAL ENGINEERING   (United States)

^b School of Industrial Engineering   (United States)

^c PURDUE UNIVERSITY   (United States)

Author keywords

Empirical testing; Heuristic decomposition; Scheduling

Indexed keywords

COMPUTATIONAL REQUIREMENTS; EMPIRICAL TESTING; HEURISTIC DECOMPOSITION; WAFER FABRICATION;

COMPUTATION THEORY; DECISION MAKING; HEURISTIC METHODS; MATHEMATICAL MODELS; OPTIMIZATION; PROBLEM SOLVING; SEMICONDUCTOR DEVICE MANUFACTURE;

SCHEDULING;

EID: 33646742941     PISSN: 08946507     EISSN: None     Source Type: Journal    
DOI: 10.1109/TSM.2006.873510     Document Type: Article

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