Digital III-Vs review

III-Vs Review

Volumn 19, Issue 3, 2006, Pages 18-22

  Cooke, Mike ^a  

^a NONE

Author keywords

[No Author keywords available]

Indexed keywords

COSTS; DIGITAL STORAGE; ECONOMIC AND SOCIAL EFFECTS; LOGIC CIRCUITS; RELIABILITY; SEMICONDUCTOR DEVICES;

DIGITAL DATA; PERIODIC BOOMS; SPECIALISED APPLICATIONS; TECHNOLOGICAL ADVANCES;

DIGITAL DEVICES;

EID: 33646714660     PISSN: 09611290     EISSN: None     Source Type: Journal    
DOI: 10.1016/S0961-1290(06)71588-5     Document Type: Article

References (6)

1. “Novel InSb-based Quantum Well Transistors for Ultra-High Speed, Low Power Logic Applications”, T. Ashley et al., Qinetic, Intel Corp.
2. 6.5 “Improved Sub-10-nm CMOS Devices with Elevated Source/Drain Extensions by Tunneling Si-Selective-Epitaxial-Growth”, H. Wakabayashi, et al., NEC Corp., NEC Electronics Corp., NEC Informatec Systems Ltd.
3. 11.5 Wrap-Gated InAs Nanowire Field Effect Transistor, L.-E. Wernersson, et al., Lund University, Chalmers University of Technology, QuMat Technologies.
4. 32.1 “85nm Gate Length Enhancement and Depletion mode InSb Quantum Well Transistors for Ultra High Speed and Very Low Power Digital Logic Applications”, S. Datta, Intel Corporation, QinetiQ.
5. 32.2 “Performance Evaluation of 50 nm In0.7Ga0.3As HEMTs For Beyond-CMOS Logic Applications”, D. H. Kim, et al., MIT, Seoul National University.
6. 32.3 “Monolithic Integration of Enhancement- and Depletion-mode AlGaN/GaN HEMTs for GaN Digital Integrated Circuits”, Y. Cai, Hong Kong University of Science and Technology.