Explicit modelling of the double-gate MOSFET with VHDL-AMS

International Journal of Numerical Modelling: Electronic Networks, Devices and Fields

Volumn 19, Issue 3, 2006, Pages 239-256

  Prégaldiny, Fabien ^a   Krummenacher, François ^b   Diagne, Birahim ^a   Pêcheux, François ^c   Sallese, Jean Michel ^b   Lallement, Christophe ^a,d  

^a UNIVERSITÉ DE STRASBOURG   (France)

^b EPFL   (Switzerland)

^c SORBONNE UNIVERSITÉ   (France)

^d ENSPS Engineering School of Strasbourg   (France)

Author keywords

Compact modelling; DG MOSFET; EKV; Numerical inversion; VHDL AMS

Indexed keywords

CHARGE DENSITY; COMPACT MODELING; DG MOSFET; EKV; NUMERICAL INVERSION; VHDL-AMS;

ALGORITHMS; COMPUTATION THEORY; COMPUTER SIMULATION; MATHEMATICAL MODELS;

MOSFET DEVICES;

EID: 33646711006     PISSN: 08943370     EISSN: 10991204     Source Type: Journal    
DOI: 10.1002/jnm.609     Document Type: Article

References (16)

1. Balestra F, Cristoloveanu S, Benachir M, Brini J, Elewa T. Double-gate silicon-on-insulator transistor with volume inversion: a new device with greatly enhanced performance. IEEE Electron Device Letters 1987; 8(9): 410-412.
2. Frank DJ, Dennard RH, Nowak E, Solomon PM, Taur Y, Wong H-SP. Device scaling limits of Si MOSFETs and their application dependencies. Proceedings of the IEEE 2001; 89(3):259-288.
3. Ge L, Fossum JG. Analytical modelling of quantization and volume inversion in thin Si-film DG MOSFETs. IEEE Transactions on Electron Devices 2002; 49(2):287-294.
4. International Technology Roadmap for Semiconductors: 2004 Update. http://public.itrs.net/[May 2005].
5. Baccarani G, Reggiani S. A compact double-gate MOSFET model comprising quantum-mechanical and nonstatic effects. IEEE Transactions on Electron Devices 1999; 46(8): 1656-1666.
6. Taur Y. An analytical solution to a double-gate MOSFET with undoped body. IEEE Electron Device Letters 2000; 21(5):245-247.
7. Fossum JG, Ge L, Chiang MH, Trivedi VP, Chowdhury MM, Mathew L, Workman GO, Nguyen BY. A process/physics-based compact model for nonclassical CMOS device and circuit design. Solid-State Electronics 2004; 48:919-926.
8. Taur Y. Analytic solutions of charge and capacitance in symmetric and asymmetric double-gate MOSFETs. IEEE Transactions on Electron Devices 2001; 48(12):2861-2869.
9. Taur Y, Liang X, Wang W, Lu H. A continuous, analytic drain-current model for DG MOSFETs. IEEE Electron Device Letters 2004; 25(2): 107-109.
10. Sallese JM, Krummenacher F, Prégaldiny F, Lallement C, Roy A, Enz C. A design oriented charge-based current model for symmetric DG MOSFET and its correlation with the EKV formalism. Solid-State Electronics 2005; 49(3):485-489.
11. Enz C, Krummenacher F, Vittoz E. An analytical MOS transistor model valid in all regions of operation and dedicated to low-voltage and low-current applications. Journal of Analog Integrated Circuits and Signal Processing 1995; 8:83-114.
12. Sallese JM, Bucher M, Krummenacher F, Fazan P. Inversion charge linearization in MOSFET modelling and rigorous derivation of the EKV compact model. Solid-State Electronics 2003; 47(4):677-683.
13. Sallese JM, Porret AS. A novel approach to charge-based non-quasi-static model of the MOS transistor valid in all modes of operation. Solid-State Electronics 2000; 44:887-894.
14. Prégaldiny F, Krummenacher F, Sallese JM, Diagne B, Lallement C. An explicit quasi-static charge-based compact model for symmetric DG MOSFET. To be presented to Nanotech 2006, WCM, Boston, U.S.A., 7-11 May 2006.
15. 1076.1-1999 IEEE Standard VHDL Analog and Mixed-Signal Extensions Language Reference Manual. IEEE Press, 1999. ISBN 0-7381-1640-8.
16. Pêcheux F, Lallement C, Vachoux A. VHDL-AMS and Verilog-AMS as alternative hardware description languages for efficient modelling of multi-discipline systems. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 2005; 24(2):204-224.