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Volumn 3740 LNCS, Issue , 2005, Pages 3-14

Efficient voltage scheduling and energy-aware co-synthesis for real-time embedded systems

Author keywords

[No Author keywords available]

Indexed keywords

EMBEDDED SYSTEMS; LOGIC DESIGN; SCHEDULING; SELF ORGANIZING MAPS;

EID: 33646520547     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/11572961_2     Document Type: Conference Paper
Times cited : (2)

References (20)
  • 1
    • 0142154052 scopus 로고    scopus 로고
    • A general time model for the specification and design of embedded real-time systems
    • Münzenberger, R., Dörfel, M., Hofmann, R., and Slomka, F.: A General Time Model for the Specification and Design of Embedded Real-Time Systems. Microelectronics Journal, vol. 34, (2003). 989-1000.
    • (2003) Microelectronics Journal , vol.34 , pp. 989-1000
    • Münzenberger, R.1    Dörfel, M.2    Hofmann, R.3    Slomka, F.4
  • 2
    • 4944235863 scopus 로고    scopus 로고
    • Characterizing power consumption and delay of functional/library components for hardware/software co-design of embedded systems
    • Geneva
    • Mohsen, A., and Hofmann, R.: Characterizing Power Consumption and Delay of Functional/Library Components for Hardware/Software Co-design of Embedded Systems. In the 15th IEEE International Workshop on Rapid System Prototyping (RSP'04), Geneva, (2004) 45-52.
    • (2004) 15th IEEE International Workshop on Rapid System Prototyping (RSP'04) , pp. 45-52
    • Mohsen, A.1    Hofmann, R.2
  • 8
    • 4544327551 scopus 로고    scopus 로고
    • System-level design methods for low energy architectures containing variable voltage processors
    • November 12, Cambridge (MA), US
    • Gruian, F.: System-Level Design Methods for Low Energy Architectures Containing Variable Voltage Processors. In Proc. of Power-Aware Computing Systems Workshop, November 12, Cambridge (MA), US, (2000).
    • (2000) Proc. of Power-aware Computing Systems Workshop
    • Gruian, F.1
  • 13
    • 0031644257 scopus 로고    scopus 로고
    • The simulation and evaluation of dynamic voltage scaling algorithms
    • Monterey, CA USA, August 10-12, ACM
    • Pering, T., Burd, T., and Broderson, R.: The Simulation and Evaluation of Dynamic Voltage Scaling Algorithms. ISELPED 98, (Monterey, CA USA, August 10-12, 1998), ACM, (2000) 76-81.
    • (1998) ISELPED 98 , pp. 76-81
    • Pering, T.1    Burd, T.2    Broderson, R.3
  • 16
    • 2942547409 scopus 로고    scopus 로고
    • SPEA2: Improving the strength pareto evolutionary algorithm for multiobjective optimization
    • CIMNE, Barcelona, Spain
    • Zitzler, E., Laumanns, M., and Thiele, L.: SPEA2: Improving the Strength Pareto Evolutionary Algorithm for Multiobjective Optimization. Evolutionary Methods for Design, Optimization, and Control, CIMNE, Barcelona, Spain, (2002) 95-100.
    • (2002) Evolutionary Methods for Design, Optimization, and Control , pp. 95-100
    • Zitzler, E.1    Laumanns, M.2    Thiele, L.3
  • 17
    • 0036504666 scopus 로고    scopus 로고
    • Performance-effective and low-complexity task scheduling for heterogeneous computing
    • Topcuouglu, H., Hariri, S., and Wu, M.: Performance-effective and Low-complexity Task Scheduling for Heterogeneous Computing. IEEE Transactions on Parallel and Distributed Systems, Vol. 13, No. 3, (2002) 260-274.
    • (2002) IEEE Transactions on Parallel and Distributed Systems , vol.13 , Issue.3 , pp. 260-274
    • Topcuouglu, H.1    Hariri, S.2    Wu, M.3
  • 18
    • 33646514568 scopus 로고    scopus 로고
    • The Wallenberg Laboratory for Research on Information Technology and Autonomous Systems. Available at http://www.ida.liu.se/ext/witas.


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.