VLSI architecture design and implementation for BLOWFISH block cipher with secure modes of operation

ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings

Volumn 4, Issue , 2001, Pages 57-60

  Lai, Yeong Kang ^a   Shu, Yu Chuan ^a  

^a NATIONAL DONG HWA UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

BLOCK CIPHERS; CLOCK RATE; CMOS TECHNOLOGY; DATA ENCRYPTION; HIGH-SPEED NETWORKING; MODES OF OPERATION; PROTOTYPE CHIP; VLSI ARCHITECTURES;

CMOS INTEGRATED CIRCUITS; SECURITY OF DATA;

CRYPTOGRAPHY;

EID: 33646502717     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCAS.2001.922168     Document Type: Conference Paper

References (5)

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2. M.C.J. Lin and Y.L. Lin, " A VLSI implementation FISH block cipher has been presented. It integrates loop-of the blowfish encryption/decryption algorithm," in folding technique and foursecure modes (ECB, CBC2.CFB2 Proc. IEEE ASP-DAC, pp. 1-2,2000.
3. S. Wolter, H. Matz, A. Schubert, and R. Laur, " On the VLSI implementation of the international data encryption algorithm IDEA," in Proc. Int. Symp. Circuits and Systems, vol. 1, pp.397-400, 1995.
4. R. Zimmermann, A. Curiger, H. Bonnenberg, H. Kaeslin, N. Felber, and W. Fichtner, "A 177 Mb/s VLSI implementation of the international data encryption algorithm," IEEE J. Solid-State Circuits, vol. 29, no. 3, pp. 303-307, Mar, 1994.
5. A. Schubert, V. Meyer, and W.Anheier, " Reusable cryptographic VLSI core based on the safer K-128 algorithm with 251.8 Mbit/s throughput," in IEEE Workshop on Signal Processing Systems, pp. 437-446, 1998.