A 0.7-2-GHz self-calibrated multiphase delay-locked loop

IEEE Journal of Solid-State Circuits

Volumn 41, Issue 5, 2006, Pages 1051-1061

  Chang, Hsiang Hui ^a,b,c   Chang, Jung Yu ^a,b   Kuo, Chun Yi ^a,b,d   Liu, Shen Iuan ^a,b,e  

^a IEEE   (Taiwan)

^b NATIONAL TAIWAN UNIVERSITY   (Taiwan)

^c MEDIATEK INC   (Taiwan)

^d Afa Technologies Inc

^e NTU ^*  (Taiwan)

Author keywords

Calibration; Delay locked loop (DLL); Multiphase

Indexed keywords

DELAY-LOCKED LOOP (DLL); DIGITAL CALIBRATION CIRCUITS; MULTIPHASE; POWER DISSIPATIONS;

CMOS INTEGRATED CIRCUITS; ELECTRIC POTENTIAL; ERROR ANALYSIS; NATURAL FREQUENCIES; THERMAL EFFECTS;

CALIBRATION;

EID: 33646421401     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2006.874036     Document Type: Article

References (20)

1. R. B. Watson. Jr. and R. B. Iknaian. "Clock buffer chip with multiple target automatic skew compensation," IEEE J. Solid-State Circuits, vol. 30. pp. 1267-1276. Nov. 1995.
2. C. H. Kim et al., "A 64-Mbit, 640-Mbyte/s bidirectional data strobed, double-data-rate SDRAM with a 40-mW DLL for a 256-Mbyte memory system." IEEE J. Solid-State Circuits, vol. 33, pp. 1703-1710. Nov. 1998.
3. Y. Moon, J. Choi, K. Lee, D. K. Jeong, and M. K. Kim, "An all-analog multiphase delay-locked loop using a replica delay line for wide-range operation and low-jitter performance," IEEE J. Solid-State Circuits, vol. 35, pp. 377-384, Mar. 2000.
4. G. Chien and P. Gray, "A 900 MHz local oscillator using a DLL-based frequency multiplier technique for PCS applications," in IEEE International Solid-State Circuits Conference, Feb. 2000, pp. 202-203.
5. C. Kim, I.-C. Hwang, and S.-M. Kang, "A low-power small-area ± 7.28-ps-jitter 1-GHz DLL-based clock generator," IEEE J. Solid-State Circuits, vol. 37, pp. 1414-1420, Dec. 2002.
6. X. Maillard, F. Devisch, and M. Kuijk, "A 900-Mb/s CMOS data recovery DLL using half-frequency clock," IEEE J. Solid-State Circuits, vol. 37, pp. 711-715, June 2002.
7. C.-K. K. Yang, R. Farjad-Rad, and M. A. Horowitz, "A 0.5-μm CMOS 4.0-Gbit/s serial link transceiver with data recovery using oversampling, "IEEE J. Sotid-State Citruits, vol. 33, pp. 713-721, May 1998.
8. M. J. Lee. W. J. Dally, J. W. Poulton, P. Chiang, and S. E. Greenwood, "An 84-mW 4Gb/s clock and data recovery circuit for serial link applications," in Symposium on VLSI Circuits, 2001, pp. 149-152.
9. C. H. Park. O. Kim, and B. Kim, "A 1.8-GHz self-calibrated phase-locked loop with precise I/Q matching." IEEE J. Solid-State Circuits, vol. 36, pp. 777-783, May 2001.
10. L. Wu and W. C. Black, Jr., "A low-jitter skew-calibrated multi-phase clock generator for time-interleaved applications." in International Solid-State Circuits Conference, Feb. 2001, pp. 396-399.
11. S. H. Wang, J. Gil, I. Kwon. H. K. Ahn, H. Shin, and B. Kim, "A 5-GHz band I/Q clock generator using a self-calibration technique," in 28th European Solid-State Circuits Conference, Sept. 2002, pp. 807-810.
12. F. Baronti, D. Lunardini, R. Roncella, and R. Saletti, "A self-calibrating delay-locked delay line with shunt-capacitor circuit scheme." IEEE J. Solid-State Circuits, vol. 39, pp. 384-387, Feb. 2004.
13. H. H. Chang, C. H. Sun, and S. I. Liu, "A low jitter and precise multiphase delay-locked loop using shifted averaging VCDL," in International Solid-State Circuits Conference, Feb. 2003, pp. 434-435.
14. W. S. T. Yan and H. C. Luong, "A 900-MHz CMOS low-phase-noise voltage-controlled ring oscillator," IEEE Trans. Circuits and System II, vol. 48, pp. 216-221, Feb. 2001.
15. A. Alvanpour, R. K. Krishnamurthy, D. Eckerbert, S. Apperson, B. Bloechel, and S. Borkar, "A 3.5 GHz, 32 mW 150 nm multiphase clock generator for high-performance microprocessors," in IEEE International Solid-State Circuits Conference, Feb. 2003, pp. 112-113, and 482.
16. B. Razavi, Design of Integrated Circuits for Optical Communications.: McGraw- Hill, 2003, pp. 297-298.
17. J. Lee, K. S. Kundert, and B. Razavi, "Analysis and modeling of bang-bang clock and data recovery circuits." IEEE J. Solid-Stale Circuits, vol. 39, pp. 1571-1580, Sep. 2004.
18. A. Momtaz, C. Jun, M. Caresosa, A. Hairapetian, D. Chung. K. Vakilian, M. Green, T. Wee-Guan. J. Keh-Chee, I. Fujimori, and C. Yijun, "A fully integrated SONET OC-48 transceiver in standard CMOS," IEEE J. Solid-Stale Circuits, vol. 36. pp. 1964-1973, Dec. 2001.
19. T. Saeki, M. Mitsuishi, H. Iwaki, and M. Tagishi, "A 1.3-cycle Lock time, non-PLL/DLL clock multiplier based on direct clock cycle interpolation for "clock on demand"." IEEE J. Solid-Stale Circuits, vol. 35. pp. 1581-1590, Nov. 2000.
20. R. C. H. van de Beek, E. A. M. Klumperink, C. S. Vaucher, and B. Nauta, "Low jitter clock multiplication: a comparison between PLLs and DLLs," IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, vol. 49, pp. 555-556, Aug. 2002.