Application-specific customisation of multi-threaded soft processors

IEE Proceedings: Computers and Digital Techniques

Volumn 153, Issue 3, 2006, Pages 173-180

  Dimond, R ^a   Mencer, O ^a   Luk, W ^a  

^a IMPERIAL COLLEGE LONDON   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; BENCHMARKING; COMPUTER ARCHITECTURE; CRYPTOGRAPHY; FIELD PROGRAMMABLE GATE ARRAYS; LOGIC DESIGN; LOGIC PROGRAMMING;

CRYPTOGRAPHY BENCHMARKS; DESIGN SPACE EXPLORATION; MICROBLAZE PROCESSOR; MULTI-THREADED MICROPROCESSORS;

MICROPROCESSOR CHIPS;

EID: 33646406294     PISSN: 13502387     EISSN: None     Source Type: Journal    
DOI: 10.1049/ip-cdt:20050177     Document Type: Article

References (21)

1. Seng, S.P., Luk, W., and Cheung, P.Y.K.: ' Runtime adaptive flexible instruction processors ', Proc. Field-Programmable Logic and Applications, 2002
2. Xtensa extensible processor. http://www.tensilica.com
3. ARCtangent extensible processor. http://www.arccores.com
4. Ungerer, T., Robic, B., and Silc, J.: ' A survey of processors with explicit multithreading ', ACM Comput. Surv., 2003, 35, (1), p. 29-63
5. ACE Associated Computer Experts bv. CoSy compiler development system. http://www.ace.nl
6. Dimond, R., Mencer, O., and Luk, W.: ' CUSTARD-a customisable threaded FPGA soft processor and tools ', Proc. Field Programmable Logic and Applications (FPL), August 2005, p. 1-6
7. Xilinx. MicroBlaze Hardware Reference Guide, March 2002. http://www.xilinx.com
8. Altera. 'Custom instructions for the Nios embedded processor', September 2002. Application Note 118
9. Norden, E.: ' A multithreading extension for low-power, low-cost applications (tricore processor) ', Embedded Processor Forum Presentation, 2003
10. META - RISC/DSP core with hardware multi-threading. http://www.metagence. com
11. Watcharawitch, P., and Moore, S.: ' JMA: the java-multithreading architecture for embedded processors ', Int. Conf. on Computer Design (ICCD), September 2002, The IEEE Computer Society
12. Yiannacouras, P., Rose, J., and Steffan, J.G.: ' The microarchitecture of FPGA-based soft processors ', Proc. Compilers, Architecture and Synthesis for Embedded Systems (CASES), September 2005
13. Atasu, K., Dündar, G., and Özturan, C.: ' An integer linear programming approach for identifying instruction-set extensions ', Proc. Hardware/Software Codesign and System Synthesis (CODES+ISSS), September 2005, p. 172-177
14. Brisk, P., Kaplan, A., Kastner, R., and Sarrafzadeh, M.: ' Instruction generation and regularity extraction for reconfigurable processors ', Proc. Compilers, Architecture and Synthesis for Embedded Systems (CASES), October 2002, p. 262-269
15. Sun, F., Ravi, S., Raghunathan, A., and Jha, N.K.: ' Custom-instruction synthesis for extensible-processor platforms ', IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., 2004, 23, (2), p. 216-228
16. Biswas, P., Choudhary, V., Atasu, K., Pozzi, L., Ienne, P., and Dutt, N.: ' Introduction of local memory elements in instruction set extensions ', Proc. DAC, June 2004, p. 729-734
17. Handel-C language reference manual. http://www.celoxica.com
18. Dimond, R., Mencer, O., and Luk, W.: ' Automating processor customisation: Optimized memory access and resource sharing ', Proc. Design, Automation and Test in Europe (DATE), 2006
19. Breuer, M.A.: ' Generation of optimal code for expressions via factorisation ', Commun. ACM, 1969, 12, (6), p. 333-340
20. Austin, T., Larson, E., and Ernst, D.: ' Simple Scaler: an infrastructure for computer system modeling ', Computer, 2002, 35, (2), p. 59-67
21. Guthaus, M.R.: et al. ' MiBench: a free, commercially representative embedded benchmark suite ', Proc. IEEE 4th Annual Workshop on Workload Characterisation, Austin, TX, December 2001