Invariant checking combining forward and backward traversal

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 3312, Issue , 2004, Pages 414-429

  Stangier, Christian ^a   Sidle, Thomas ^a  

^a FUJITSU LABORATORIES OF AMERICA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER AIDED DESIGN;

DYNAMIC APPROACHES; FORWARD-AND-BACKWARD; INITIAL STATE; INVARIANT CHECKING; POTENTIAL ERRORS; REDUNDANT COMPUTATION; TWO DIRECTIONS; VARIABLE ORDER;

FORMAL METHODS;

EID: 33646397486     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/978-3-540-30494-4_29     Document Type: Article

References (13)

1. R. E. Bryant, Graph-Based Algorithms for Boolean Function Manipulation, IEEE Transactions on Computers, C-35,1986.
2. J. R. Burch, E. M. Clarke and D. E. Long, Symbolic Model Checking with partitioned transition relations, Proc. of Int. Conf. on VLSI, 1991.
3. R. K. Brayton, G. D. Hachtel, A. L. Sangiovanni-Vincentelli, F. Somenzi, A. Aziz, S. Cheng, S. A. Edwards, S. P. Khatri, Y. Kukimoto, A. Pardo, S. Qadeer, R. K. Ranjan, S. Sarwary, T. R. Shiple, G. Swamy and T. Villa, VIS: A System for Verification and Synthesis, Proc. of Computer Aided Verification (CAV'96), 1996.
4. O. Coudert, C. Berthet and J. C. Madre, Verification of Synchronous Machines using Symbolic Execution, Proc. of Workshop on Automatic Verification Methods for Finite State Machines, LNCS 407, Springer, 1989.
5. G. Cabodi, P. Camurati and S. Quer, Efficient State Space Pruning in Symbolic Backward Traversal, Proc. of ICCD, 1994.
6. G. Cabodi, S. Nocco and S. Quer, Mixing Forward and Backward Traversals in GuidedPrioritized BDD-Based Verification, Proc. of CAV, 2002.
7. S. Fortune, J. Hopcroft and E. Schmidt, The Complexity of Equivalence and Containment for Free Single Variable Program Schemes, Proc. of ICALP, 1978.
8. S.O. Govindaraju and D. L. Dill, Verification by approximate forward and backward reachability, Proc. ICCAD, 1998.
9. H. Iwashita and T. Nakata, Forward Model Checking Techniques Oriented to Buggy Designs, Proc. ICCAD, 1997.
10. R. K. Ranjan, A. Aziz, R. K. Brayton, C. Pixley and B. Plessier, Efficient BDD Algorithms for Synthesizing and Verifying Finite State Machines, Proc. of Int. Workshop on Logic Synthesis (IWLS'95), 1995.
11. F. Somenzi, CUDD: CU Decision Diagram Package, ftp://vlsi.colorado.edu/ pub/.
12. D. E. Thomas and P. Moorby, The Verilog Hardware Description Language, Kluwer, 1991.
13. VIS Verilog Benchmarks, vlsi.colorado.edu/~vis/