A new model for four-terminal junction field-effect transistors

Solid-State Electronics

Volumn 50, Issue 3, 2006, Pages 422-428

  Ding, Hao ^a   Liou, Juin J ^a   Green, Keith ^b   Cirba, Claude R ^b  

^a UNIVERSITY OF CENTRAL FLORIDA   (United States)

^b TEXAS INSTRUMENTS   (United States)

Author keywords

Analog circuit; Compact modeling; Field effect transistors

Indexed keywords

CAPACITANCE; COMPUTER SIMULATION; DATA REDUCTION; MATHEMATICAL MODELS;

ANALOG CIRCUIT; COMPACT MODELING; STEADY-STATE CHARACTERISTICS;

FIELD EFFECT TRANSISTORS;

EID: 33646095768     PISSN: 00381101     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.sse.2006.01.001     Document Type: Article

References (15)

1. Manghisoni M., et al. JFET front end circuits integrated in a detector grade silicon substrate. IEEE Trans Nucl Sci 50 (2003) 942
2. Yoshida N, Ishizaka M et al. A 10 Gb/s optical transmitter module with a built-in modulator driver IC and a receiver module with a built-in preamplifier IC. In: Gallium arsenide integrated circuit (GaAs IC) symposium, 1999. p. 287-90.
3. Grebene A.B., and Ghandhi S.K. General theory for operation of the junction-gate FET. Solid-State Electron 12 (1969) 573-589
4. Juin J. Liou. Advanced semiconductor device physics and modeling, Artech House, 1994.
5. Antognetti P., and Massobrio G. Semiconductor device modeling with SPICE (1987), New York, McGraw-Hill
6. Taki T. Approximation of junction field-effect transistor characteristics by a hyperbolic function. IEEE J Solid-State Circ SC-13 (1978) 724
7. Liou J.J., and Yue Y. An improved model for four-terminal junction field-effect transistors. IEEE Trans Electron Dev 43 (1996)
8. Paul Van Halen. A physical spice-compatible dual-gate JFET model. In: Proceedings of the 33rd midwest symposium on circuit and systems, vol. 2, August 1990. p. 715.
9. Colin C. McAndrew. An accurate JFET and 3-terminal diffused resistor model, In: Nanotech compact modeling workshop, vol. 2, 2004.
10. BSIM4.2.1 Manual, 2001.
11. Brewer R.J. The barrier mode behavior of a junction FET at low drain currents. Solid-State Electron 18 (1975) 1013-1017
12. ∞-continuous depletion capacitance model. IEEE Trans Comput Aid Des Integr Circ Sys 12 (1993)
13. Van Mieghem P., Mertens R.P., and Van Overstraeten R.J. Theory of the junction capacitance of an abrupt diode. J Appl Phys 67 (1990)
14. Van Halen P. A new semiconductor junction diode space charge layer capacitance model, In: Proceedings of IEEE BCTM, 1988. p. 168-71.
15. Spectre circuit simulator device model equations, Version 5.0, December 2002.