Front- to back-side overlay optimization after wafer bonding for 3D integration

Microelectronic Engineering

Volumn 83, Issue 4-9 SPEC. ISS., 2006, Pages 1229-1232

  Marinier, Laurent ^a   van Noort, Wibo ^a   Pellens, Rudy ^b   Sutedja, Budiman ^b   Dekker, Ronald ^a   van Zeijl, Henk ^c  

^a PHILIPS RESEARCH LABORATORIES   (Netherlands)

^b ASML   (Netherlands)

^c DELFT UNIVERSITY OF TECHNOLOGY   (Netherlands)

Author keywords

3D IC; 3D integration; Alignment; Lithography; MEMS; Overlay; Substrate transfer; Wafer bonding

Indexed keywords

BONDING; GLASS; LITHOGRAPHY; MICROELECTROMECHANICAL DEVICES; OPTIMIZATION; SILICON; SUBSTRATES;

3D IC; 3D INTEGRATION; OVERLAY; SUBSTRATE TRANSFER; WAFER BONDING;

SILICON WAFERS;

EID: 33646072802     PISSN: 01679317     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.mee.2006.01.127     Document Type: Article

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