Model-order reduction using variational balanced truncation with spectral shaping

IEEE Transactions on Circuits and Systems I: Regular Papers

Volumn 53, Issue 4, 2006, Pages 879-891

  Heydari, Payam ^a   Pedram, Massoud ^b  

^a University of California at Irvine   (United States)

^b University of Southern California ^*  (United States)

Author keywords

Balanced truncation; Interconnect; Lur'e equations; Model order reduction; Passivity; Process variation; Spectral shaping

Indexed keywords

ALGORITHMS; COUPLED CIRCUITS; PASSIVE NETWORKS; STATISTICAL METHODS; TIME DOMAIN ANALYSIS; TRANSFER FUNCTIONS;

BALANCED TRUNCATION; LUR'E EQUATIONS; MODEL-ORDER REDUCTION; PASSIVITY; PROCESS VARIATION; SPECTRAL SHAPING;

INTEGRATED CIRCUIT MANUFACTURE;

EID: 33645832199     PISSN: 10577122     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCSI.2005.859772     Document Type: Article

References (28)

1. S. Oh, W. Jung, J. Kong, and K. Lee, "Interconnect modeling for VLSI," in Proc. Int. Conf. Simulation of Semiconductor Processes and Devices, 1999, pp. 203-206.
2. L. T. Pillage and R. A. Rohrer, "Asymptotic waveform evaluation for timing analysis," IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., vol. 9, no. 4, pp. 352-366, Apr. 1990.
3. C. Ratzlaff and L. T. Pillage, "RICE: Rapid interconnect circuit evaluation using AWE," IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., vol. 13, no. 6, pp. 763-776, Jun. 1994.
4. K. J. Kerns and A. T. Yang, "Stable and efficient reduction of large, multiport RC networks by pole analysis via congruence transformations," IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., vol. 16, pp. 734-744, 1997.
5. P. Feldmann and R. W. Freund, "Efficient linear circuit analysis by Pade approximation via the Lanczos process," IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., vol. 14, pp. 639-649, May 1995.
6. A. Odabasioglu, M. Celik, and L. T. Pileggi, "PRIMA: Passive reduced-order interconnect macromodeling algorithm," IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., vol. 17, no. 8, pp. 645-654, Aug. 1998.
7. J. Roychowdhury, "Reduced-Order modeling of time-varying systems," IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 46, no. 10, pp. 1273-1288, Oct. 1999.
8. L. Peng and L. T. Pileggi, "NORM: Compact model-order reduction of weakly nonlinear systems," in Proc. IEEE/ACM Design Autom. Conf., Jun. 2003, pp. 427-477.
9. ∞-error bounds," Int. J. Contr., vol. 39, no. 6, pp. 1115-1193, 1984.
10. P. Rabiei and M. Pedram, "Model-order reduction of large circuits using balanced truncation," in Proc. IEEE ASP-DAC, 1999, pp. 237-240.
11. J. Li, F. Wang, and J. White, "An efficient Lyapunov equation-based approach generating reduced-order models of interconnect," in Proc. 36th ACM/IEEE Design Autom. Conf., 1999, pp. 1-6.
12. J. Li and J. White, "Efficient model reduction of interconnect via approximate system Grammians," Proc. IEEE/ACM ICCAD'99, pp. 380-384, 1999.
13. J. R. Phillips, L. Daniel, and L. M. Silveira, "Guaranteed passive balancing transformations for model-order reduction," IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., vol. 22, no. 8, pp. 1027-1041, Aug. 2003.
14. A. Lu and E. L. Wachspress, "Solution of Lyapunov equations by alternating direction implicit," Comput. Math. Appl., vol. 21, no. 9, pp. 43-58, Jun. 1991.
15. N. Ellner and E. L. Wachspress, "Alternating direction implicit iteration for systems with complex spectra," SIAM J. Numer., Anal., vol. 28, no. 3, pp. 859-870, Jun. 1991.
16. G. Wang, V. Sreeram, and W. Q. Liu, "A new frequency-weighted balanced truncation method and an error bound," IEEE Trans. Autom. Contr., vol. 44, no. 9, pp. 1734-1737, Sep. 1999.
17. V. Sreeram, "On the properties of frequency weighted balanced truncation techniques," in Proc. Amer. Contr. Conf., vol. 3, May 2002, pp. 1753-1754.
18. P. Heydari and M. Pedram, "Balanced truncation with spectral shaping for RLC interconnects," in Proc. IEEE ASP-DAC, Jan. 2001, pp. 203-208.
19. Y. Liu, L. T. Pileggi, and A. Strojwas, "Model order-reduction of RC(L) interconnect including variational analysis," in Proc. 36th IEEE/ACM Proc. Design Autom. Conf., Jun. 1999, pp. 201-206.
20. G. H. Golub and C. Van Loan, Matrix Computation. Baltimore, MD: Johns Hopkins University Press, 1996, pp. 390-405.
21. P. Heydari and M. Pedram, "Model reduction of variable geometry interconnects using variational spectrally-weighted balanced truncation," in Proc. IEEE ICCAD, San Jose, CA, Nov. 2001.
22. L. Daniel, C. S. Ong, S. C. Low, K. H. Lee, and J. White, "A multiparameter moment matching model reduction approach for generating geometrically parameterized interconnect performance models," IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., vol. 23, no. 5, pp. 678-93, May 2004.
23. M. G. Safanov and R. Y. Chiang, "A Schur method for balanced truncation model reduction," in Proc. Amer. Contr. Conference, vol. 2, 1988, pp. 1036-1040.
24. P. J. Antsaklis and A. N. Micel, Linear Systems. New York: McGraw-Hill, 1997.
25. O. S. Nakagawa, S.-Y. Oh, and G. Ray, "Modeling of pattern-dependent on-chip interconnect geometry variation of deep-submicron process and design technology," in Tech. Dig. IEEE Int. Electron Devices Meeting, 1997, pp. 137-141.
26. O. S. Nakagawa, N. Chang, S. Lin, and D. Sylvester, "Circuit impact and skew corner analysis of stochastic process variation in global interconnect," in Proc. IITC, 1999, pp. 230-232.
27. S. R. Nassif, "Modeling and forecasting of manufacturing variations," in Proc. 5th Int. Workshop Statistical Metrology, 2000, pp. 2-10.
28. Y. I. Ismail, E. G. Friedman, and J. L. Neves, "Equivalent elmore delay for RLC trees," in Proc. IEEE/ACM Des. Autom. Conf., Jun. 1999, pp. 715-720.