VLSI implementation of a low-error-floor and capacity-approaching low-density parity-check code decoder with multi-rate capacity

GLOBECOM - IEEE Global Telecommunications Conference

Volumn 3, Issue , 2005, Pages 1261-1266

  Yang, Lei ^a   Liu, Hui ^a   Shi, C J Richard ^a  

^a University of Washington   (United States)

Author keywords

(forward Error Correction) FEC; (Low Density Parity Check) LDPC; (Orthogonal Frequency Division Multiplexing) OFDM; (Signal to Noise Ratio) SNR; Block Error Rate; Cycle Elimination; FPGA; VLSI

Indexed keywords

BLOCK ERROR RATE; CYCLE ELIMINATION; FORWARD ERROR CORRECTION (FEC); LOW DENSITY PARITY CHECK (LDPC);

ALGORITHMS; CHANNEL CAPACITY; FIELD PROGRAMMABLE GATE ARRAYS; ORTHOGONAL FREQUENCY DIVISION MULTIPLEXING; SIGNAL TO NOISE RATIO; TELECOMMUNICATION SERVICES; VLSI CIRCUITS; WIRELESS TELECOMMUNICATION SYSTEMS;

DECODING;

EID: 33645827028     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/GLOCOM.2005.1577854     Document Type: Conference Paper

References (16)

1. J. Campello, D. S. Modha, and S. Rajagopalan, "Designing LDPC Codes Using Bit-Filling", Proceeding International Conference Communications, Helsinki, Finland, pp. 55-59, 2001.
2. X. Y. Hu, E. Eleftheriou, and D. M. Arnold, "Progressive Edge-Growth Tanner Graphs", Proceeding IEEE Global Telecommunications Conference, vol. 2, pp. 995-1001, Nov. 2001.
3. H. Zhang and T. Zhang, "Design of VLSI Implementation-Oriented LDPC Codes", Proceeding IEEE Vehicular Technology Conference, vol. 1, pp. 670-673, 2003.
4. D. E. Hocevar, "LDPC Code Construction with Flexible Hardware Implementation", Proceeding IEEE International Conference on Communications, pp. 2708-2712, 2003.
5. A. Delvarathinam, E. Kim, and G. Choi, "Low-Density Parity-Check Decoder Architecture for High Throughput Optical Fiber Channels", Proceeding International Conference on Computer Design, pp. 520-525, 2003.
6. E. Boutillon, J. Castura, and F. R. Kschischang, "Decoder-first Code Design", Proceeding International Symposium Turbo Codes and Related Topics, Brest, France, pp. 459-462, Sept. 2001.
7. A.J. Blanksby and C.J. Howland, "A 690-mW 1-Gb/s 1024-b, Rate-1/2 Low-Density Parity-Check Code Decoder", IEEE Journal of Solid-State Circuits, vol. 37, no. 3, pp. 404-412, Mar. 2002.
8. T. Zhang and K. K. Parhi, 'VLSI Implementation-Oriented (3,k)-Regular Low-Density Parity-Check Codes", Proceeding IEEE Workshop on Signal Processing Systems, pp. 25-36, Sept. 2001.
9. G. Xing, M. Shen, H. Liu, et al., "An LDPC-based Terrestrial Multimedia Broadcasting (TMB) System: Design, Implementation and Experimental Results", Acoustics, Speech, and Signal Processing, vol. 4, pp. 17-21, May 2004.
10. G. Xing, M. Shen, H. Liu, et al., "An LDPC-based Terrestrial Multimedia Broadcasting (TMB) System: Design, Implementation and Experimental Results", Acoustics, Speech, and Signal Processing, vol. 4, pp. 17-21, May 2004.
11. L. Yang, H. Liu and C.-J. Richard Shi, "Code Construction and FPGA Implementation of Capacity-Approaching Low-Error-Floor Multi-Rate Low-Density Parity-Check Decoder", submitted to IEEE Transaction on Circuits and Systems.
12. A. Anastasopoulos, "A Comparison between the Sum-Product and the Min-Sum Iterative Detection Algorithms Based on Density Evolution", Proceeding IEEE Global Telecommunications Conference, vol. 2, pp. 25-29, Nov. 2001.
13. X. Y. Hu, E. Eleftheriou, and D. M. Arnold, "Efficient Implementation of the Sum-Product Algorithm for Decoding LDPC Codes", Proceeding IEEE Global Telecommunications Conference, vol. 2, pp. 1036-1036, Nov. 2001.
14. T. Tian, C. Jones, J. D. Villasenor, and R. D. Wesel, "Construction of Irregular LDPC Codes with Low Error Floors", Proceeding IEEE International Conference on Communication, vol. 5, pp. 3125-3129, May 2003.
15. T. Richardson, M. A. Shokrollahi and R. L. Urbanke, "Design of Capacity-Approaching Irregular Low-Density Parity-Check Codes", IEEE Transaction on Information Theory, vol. 47, pp. 619-637, Feb. 2001.
16. T. Richardson, "Error Floors of LDPC codes," Proceeding of 41st Allerton Conference on Communications, Control and Computing, Oct. 2003.