An enhanced BSA for floorplanning

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences

Volumn E89-A, Issue 2, 2006, Pages 528-534

  Fang, Jyh Perng ^a   Tong, Yang Shan ^b   Chen, Sao Jie ^b,c,d,e,f  

^a NATIONAL TAIPEI UNIVERSITY OF TECHNOLOGY   (Taiwan)

^b NATIONAL TAIWAN UNIVERSITY   (Taiwan)

^c Chinese Institute of Engineers   (China)

^d Chinese Institute of Electrical Engineering   (Taiwan)

^e Association for Computing Machinety

^f IEEE

Author keywords

Buffer insertion; Dominant wide bus; Floorplanning; Routing

Indexed keywords

ALGORITHMS; CONGESTION CONTROL (COMMUNICATION); FLOORS; MATHEMATICAL MODELS; PROBLEM SOLVING;

BUFFER INSERTION; DOMINANT WIDE BUS; FLOORPLANNING; ROUTING;

INTEGRATED CIRCUITS;

EID: 33645749898     PISSN: 09168508     EISSN: 17451337     Source Type: Journal    
DOI: 10.1093/ietfec/e89-a.2.528     Document Type: Article

References (11)

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