Simultaneous routing and buffering in floorplan design

International Symposium on VLSI Technology, Systems, and Applications, Proceedings

Volumn 2003-January, Issue , 2003, Pages 188-191

  Fang, Jyh Perng ^a   Tong, Yang Shan ^a   Chen, Sao Jie ^a  

^a NATIONAL TAIWAN UNIVERSITY   (Taiwan)

Author keywords

Buffer insertion; Floorptanning; Global routing

Indexed keywords

ALGORITHMS; APPLICATION SPECIFIC INTEGRATED CIRCUITS; BUFFER CIRCUITS; ITERATIVE METHODS; PROGRAMMABLE LOGIC CONTROLLERS; SYSTEM-ON-CHIP;

BUFFER INSERTION; FLOOR-PLANNING; FLOORPLAN DESIGN; FLOORPTANNING; GLOBAL ROUTING; MANHATTAN ROUTING; PROCESSING SPEED; SYSTEM ON A CHIP;

INTEGRATED CIRCUIT DESIGN;

EID: 33645748798     PISSN: 19308868     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VTSA.2003.1252584     Document Type: Conference Paper

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