An application-level methodology to guide the design of intelligent-processing, power-aware passive RFIDs

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn , Issue , 2005, Pages 5509-5512

  Alippi, Cesare ^a   Vanini, Giovanni ^a  

^a POLITECNICO DI MILANO   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

ACTIVE NODE; BIT RATES; ELECTRONICS DESIGN; ENERGY SAVING; IN-BUILDING; INTEGRATED PASSIVES; INTEGRATED SENSORS; LOW COSTS; MONITORING APPLICATIONS; POWER CONSUMPTION; POWER-AWARE; SENSOR FUSION ALGORITHMS; SIMULATION RESULT;

COST REDUCTION; SENSOR DATA FUSION; SENSOR NODES; SENSORS;

WIRELESS SENSOR NETWORKS;

EID: 33645731625     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCAS.2005.1465884     Document Type: Conference Paper

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