Memory characteristics of MOSFETs with densely stacked silicon nanocrystal layers in the gate oxide synthesized by low-energy ion beam

IEEE Electron Device Letters

Volumn 27, Issue 4, 2006, Pages 231-233

  Ng, C Y ^a   Chen, T P ^a   Ding, L ^a   Fung, S ^b  

^a NANYANG TECHNOLOGICAL UNIVERSITY   (Singapore)

^b UNIVERSITY OF HONG KONG   (Hong Kong)

Author keywords

Low energy ion beam; Memory effect; Silicon nanocrystal (nc Si)

Indexed keywords

EXTRAPOLATION; ION BEAMS; ION IMPLANTATION; NANOSTRUCTURED MATERIALS; SEMICONDUCTING SILICON; SYNTHESIS (CHEMICAL); TEMPERATURE CONTROL; THRESHOLD VOLTAGE;

GATE OXIDE; LOW-ENERGY ION BEAM; SILICON NANOCRYSTAL LAYERS;

MOSFET DEVICES;

EID: 33645635420     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/LED.2006.871183     Document Type: Article

References (14)

1. S. Tiwari, F. Rana, K. Chan, H. Hanafi, W. Chan, and D. Buchanan, "Volatile and non-volatile memories in silicon with nano-crystal storage," in IEDM Tech. Dig., 1995, pp. 521-524.
2. S. Tiwari, F. Rana, H. Hanafi, A. Harstein, E. F. Crabbe, and K. Chan, "A silicon nanocrystal based memory," Appl. Phys. Lett., vol. 68, no. 10, pp. 1377-1379, Mar. 1996.
3. Y. Shi, K. Saito, H. Ishikuro, and T. Hiramoto, "Characteristic of narrow channel MOSFET memory based on silicon nanocrystals," Jpn. J. Appl. Phys. 1, Regul. Pap. Short Notes, vol 38, no. 4B, pp. 2453-2456, Apr. 1999.
4. G. Ammendola, M. Vulpio, M. Bileci, N. Nastasi, C. Gerardi, G. Renna, I. Crupi, G. Nicotra, and S. Lombardo, "Nanocrystal metal-oxide-semiconductor memories obtained by chemical vapor deposition of Si nanocrystal," J. Vac. Sci. Technol. B, Microelectron. Process. Phenom., vol. 20, no. 5, pp. 2075-2079, Sep. 2002.
5. I. Kim, S. Han, K. Han, J. Lee, and H. Shin, "Room temperature single electron effects in a Si nano-crystal memory," IEEE Electron Device Lett., vol. 20, no. 12, pp. 630-631, Dec. 1999.
6. R. A. Rao, R. F. Steimle, M. Sadd, C. T. Swift, B. Hradsky, S. Straub, T. Merchant, M. Stoker, S. G. H. Anderson, M. Rossow, J. Yater, B. Acred, K. Harber, E. J. Prinz, B. E. White, Jr., and R. Muralidhar, "Silicon nanocrystal based memory devices for NVM and DRAM applications," Solid State Electron., vol. 48, no. 9, pp. 1463-1473, Sep. 2004.
7. 2 matrix," Jpn. J. Appl. Phys. 2, Lett., vol 39, no. 8A, pp. L792-L795, Aug. 2000.
8. S. Lombardo, B. De Salvo, C. Gerardi, and T. Baron, "Silicon nanocrystal memories," Microelectron. Eng., vol. 72, no 1-4, pp. 388-394, Apr. 2004.
9. +-implanted gate oxides," Microelectron Eng., vol. 59, no. 1-4, pp. 247-252, Nov. 2001.
10. + implanted gate oxides: From MOS capacitors to nvSRAM," Solid State Electron., vol. 46, no. 11, pp. 1729-1737, Nov. 2002.
11. P. Dimitrakis, E. Kapetanakis, D. Tsoukalas, D. Skarlatos, C. Bonafos, G. B. Asssayag, A. Cleverie, M. Perego, M. Fanciulli, V. Soncini, R. Sotgiu, A. Agarwal, M. Ameen, C. Sohl, and P. Normand, "Silicon nanocrystal memory devices obtained by ultra-low-energy ion-beam synthesis," Solid State Electron., vol. 48, no. 9, pp. 1511-1517, Sep. 2004.
12. 2," Mater. Sci. Eng. B, vol. 101, no. 1-3, pp. 14-18, Aug. 2003.
13. R. Govindaraj, R. Kesavamoorthy, R. Mythili, and B. Viswanathan, "The formation and characterization of silver clusters in zirconia," J. Appl. Phys., vol. 90, no. 2, pp. 958-963, Jul. 2001.
14. R. Ohba, N. Sugiyama, K. Uchida, J. Koga, and A. Toriumin "Non-volatile Si quantum memory with self-aligned doubly-stacked dots," in IEDM Tech. Dig., 2000, pp. 313-316.