High carrier velocity and reliability of quarter-micron SPI (Self-aligned Pocket Implantation) MOSFETs

Technical Digest - International Electron Devices Meeting, IEDM

Volumn 1992-December, Issue , 1992, Pages 699-702

  Hori, A ^a   Hiroki, A ^a   Segawa, M ^a   Hori, T ^a   Shinohara, A ^a   Yasuhira, M ^a   Akiyama, S ^a  

^a PANASONIC CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CARRIER CONCENTRATION; ELECTRON DEVICES; REFRACTORY METAL COMPOUNDS; TITANIUM COMPOUNDS;

CARRIER VELOCITY; GATE ELECTRODES; HOT CARRIER DEGRADATION; JUNCTION CAPACITANCES; LARGE ANGLE TILT IMPLANTED DRAINS; LOW IMPURITY CONCENTRATIONS; LOW-POWER DISSIPATION; SURFACE IMPURITIES;

SILICON COMPOUNDS;

EID: 33645280461     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IEDM.1992.307455     Document Type: Conference Paper

References (9)

1. A. Hori, S. Kameyama, M. Segawa, H. Shimomura and H. Ogawa, "A self-aligned pocket implantation (SPI) technology for 0. 2u. m-dual gate CMOS, " in IEDM Tech. Dig., 1991, pp. 641-644
2. T. Hori, K. Kurimoto, T. Yabu and G. Fuse, "Submicron MOSFET with LATID (large-tilt-angle implanted drain) structure, " in Tech. Dig. Symp. on VLSI Technol., 1988, pp. 15-16
3. D. A. Antoniadis and J. E. Chung, "Phisics and technology of ultra short channel MOSFET devices, " in IEDM Tech. Dig., 1991, pp. 21-24
4. M. Aoki et al., "0. 1 (im CMOS devices using low-impurity-channel transistors (LICT), " in IEDM Tech. Dig., 1990, pp. 939-941
5. R. H. Yan et al., "High performance 0. 1u. m room temperature Si MOSFETs, " in Tech. Dig. Symp. on VLSI Techno., 1992, pp. 86-87
6. T. Hori and K. Kurimoto, "A new half-micron p-channel MOSFET with LATTPS (large-lilt angle implanted punchthrough stopper" in IEDM Tech. Dig., 1988, pp. 394-397
7. S. Y. Chou and D. A. Antoniadis, "Relationship between measured and intrinsic transconductances of FET's, " IEEE Trans. on ED., vol. ED-34, 1987, pp. 448-450
8. G. J. Hu, C. Chang and Y. T. Chia, "Gate-voltage-dependent effective channel length and series resistance of LDD MOSFETs, " IEEE Trans, on ED., vol. ED-34, 1987, pp. 2469-2475
9. S. Odanaka, A. Hiroki, K. Ohe, K. Moriyama and H. Umimoto, "SMART-II: a three-dimensional CAD model for submicronmeter MOSFET's, " IEEE trans, on CAD., 1991, pp. 619-628