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Volumn , Issue , 2000, Pages 152-157

Implementation image data convolutions operations in FPGA reconfigurable structures for real-time vision systems

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER VISION; CONVOLUTION; INTERACTIVE COMPUTER SYSTEMS; RECONFIGURABLE HARDWARE; TABLE LOOKUP;

EID: 33645194486     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ITCC.2000.844199     Document Type: Conference Paper
Times cited : (19)

References (13)
  • 2
    • 0030400027 scopus 로고    scopus 로고
    • Pipelined Architecture of Reconfigurable Specialised Processors for a Real-Time Image Data Pre-Processing
    • Beijing - China, IEEE Press
    • Wiatr K.: Pipelined Architecture of Reconfigurable Specialised Processors for a Real-Time Image Data Pre-Processing. Proceedings of the IEEE International Conference on Signal Processing, Beijing - China, IEEE Press 1996, pp. 649-652
    • (1996) Proceedings of the IEEE International Conference on Signal Processing , pp. 649-652
    • Wiatr, K.1
  • 3
    • 85049845130 scopus 로고    scopus 로고
    • Pipelined Architecture of Specialised Reconfigurable Processors in FPGA Structures for Real- Time Image Data Pre-Processing
    • Vasteras - Sweden 1998, IEEE Computer Press
    • Wiatr K.: Pipelined Architecture of Specialised Reconfigurable Processors in FPGA Structures for Real- Time Image Data Pre-Processing. Proceedings of the EUROMICRO International Conference: Digital System Design: Architectures, Methods and Tools, Vasteras - Sweden 1998, IEEE Computer Press 1998, pp. 131-138
    • (1998) Proceedings of the EUROMICRO International Conference: Digital System Design: Architectures, Methods and Tools , pp. 131-138
    • Wiatr, K.1
  • 4
    • 0002902385 scopus 로고    scopus 로고
    • Constant Coefficient Multipliers for the XC4000E
    • XAPP 054 December
    • Chapman K. Constant Coefficient Multipliers for the XC4000E. Xilinx Application Note, XAPP 054 December 1996
    • (1996) Xilinx Application Note
    • Chapman, K.1
  • 6
    • 0002799279 scopus 로고
    • Fast Integer Multiplier fit in FPGA's, EDN 1993 Design Idea Winner
    • th
    • th 1994
    • (1994) EDN
    • Chapman, K.1
  • 11
    • 0031222835 scopus 로고    scopus 로고
    • Low-Area/Power Parallel FIR Digital Filter Implementations
    • Kluwer
    • Parker D.A., Parhi K.K.: Low-Area/Power Parallel FIR Digital Filter Implementations, Journal of VLSI Signal Processings 17, 75-92, Kluwer 1997
    • (1997) Journal of VLSI Signal Processings , vol.17 , pp. 75-92
    • Parker, D.A.1    Parhi, K.K.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.