The effect of die attach voiding on the thermal resistance of chip level packages

Microelectronics Reliability

Volumn 46, Issue 5-6, 2006, Pages 794-804

  Fleischer, Amy S ^a   Chang, Li Hsin ^b   Johnson, Barry C ^a  

^a Villanova University   (United States)

^b University of Arizona   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COALESCENCE; DIES; ELECTRONICS PACKAGING; HEAT RESISTANCE;

CHIP LEVEL PACKAGES; DIE ATTACH VOIDING; VOID SIZE;

MICROPROCESSOR CHIPS;

EID: 33645153130     PISSN: 00262714     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.microrel.2005.01.019     Document Type: Conference Paper

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