Implement any fractional order neural-type pulse oscillator with net-grid type analog fractance circuit

Sichuan Daxue Xuebao (Gongcheng Kexue Ban)/Journal of Sichuan University (Engineering Science Edition)

Volumn 38, Issue 1, 2006, Pages 128-132

  Pu, Yi Fei ^a   Yuan, Xiao ^a   Liao, Ke ^a   Zhou, Ji Liu ^a  

^a SICHUAN UNIVERSITY   (China)

Author keywords

Electro neurogram; Fractional calculus; Fractional order neural type pulse oscillator; Hysteretic neural type pulse oscillator; Syntony crystalloid

Indexed keywords

BIONICS; ELECTRIC NETWORK ANALYSIS; EQUIVALENT CIRCUITS; NEURAL NETWORKS;

ELECTRO-NEUROGRAM; FRACTIONAL CALCULUS; FRACTIONAL ORDER NEURAL-TYPE PULSE OSCILLATOR; HYSTERETIC NEURAL-TYPE PULSE OSCILLATOR; SYNTONY CRYSTALLOID;

OSCILLATORS (ELECTRONIC);

EID: 33645139104     PISSN: 10093087     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article

References (7)

1. Newcomb R W. Neural-type microsystem: some circuits and consideration[C]//Proc of the 1980 IEEE Conference on Circuits and Computers. New York: IEEE, 1980.
2. Kiruthi G. A hysteretic neural-type pulse oscillator[C]//Proc IEEE/ISCAS. New York: IEEE, 1983, 3: 1173-1175.
3. Barranco B L. A novel CMOS analog neural oscillator cell[J]. IEEE trans, 1989(5): 756-760.
4. Xiao Yuan. On the models of a class of programmable neural oscillator cell[C]//Proc of CHINA 1991 ICCAS. New York: IEEE, 1991: 279-281.
5. Pu Yifei, Yuan Xiao, Liao Ke, et al. A recursive net-grid-type analog fractance circuit for any order fractional calculus[C]// Proceedings of the IEEE International Conference on Mechatronics and Automation. Niagara Falls, Canada, 2005: 1375-1380.
6. Pu Yifei, Yuan Xiao, Liao Ke, et al. Structuring analog fractance circuit for 1/2 order fractional calculus[C]//Proceedings of ASICON 2005. IEEE Press, 2005: 694-698.
7. Pu Yifei, Yuan Xiao, Liao Ke, et al. Implement any fractional order multilayer dynamics associative neural network[C]//Proceedings of ASICON 2005. IEEE Press, 2005: 1075-1079.