Compact modeling and fast simulation of on-chip interconnect lines

IEEE Transactions on Magnetics

Volumn 42, Issue 4, 2006, Pages 547-550

  Ioan, Daniel ^a   Ciuprina, Gabriela ^a   Radulescu, Marius ^a   Seebacher, Ehrenfried ^b  

^a UNIVERSITY POLITEHNICA OF BUCHAREST   (Romania)

^b AMS AG   (Austria)

Author keywords

Distributed parameter circuits; Electromagnetic analysis; Finite integration technique (FIT); Integrated circuit design; Interconnects; Model extraction; Model order reduction

Indexed keywords

INTEGRATED CIRCUITS; MATHEMATICAL MODELS; MICROPROCESSOR CHIPS; NATURAL FREQUENCIES; PARAMETER ESTIMATION; SILICON; SUBSTRATES;

DISTRIBUTED PARAMETER CIRCUITS; ELECTROMAGNETIC ANALYSIS; FINITE INTEGRATION TECHNIQUE (FIT); INTEGRATED CIRCUIT DESIGN; MODEL EXTRACTION; MODEL ORDER REDUCTION;

ELECTRIC POWER SYSTEM INTERCONNECTION;

EID: 33645137379     PISSN: 00189464     EISSN: None     Source Type: Journal    
DOI: 10.1109/TMAG.2006.871466     Document Type: Article

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