Thread-parallel MPEG-2, MPEG-4 and H.264 video encoders for SoC multi-processor architectures

IEEE Transactions on Consumer Electronics

Volumn 52, Issue 1, 2006, Pages 269-275

  Jacobs, Tom R ^a   Chouliaras, Vassilios A ^a   Mulvaney, David J ^a  

^a LOUGHBOROUGH UNIVERSITY   (United Kingdom)

Author keywords

System on chip; Thread level parallelism; Video encoding

Indexed keywords

IMAGE CODING; MICROPROCESSOR CHIPS; MULTIMEDIA SYSTEMS; MULTIPROCESSING SYSTEMS; REAL TIME SYSTEMS;

MULTI-PROCESSOR ARCHITECTURE; SYSTEM-ON-CHIP; THREAD-LEVEL PARALLELISM; VIDEO ENCODERS;

IMAGE COMPRESSION;

EID: 33645010940     PISSN: 00983063     EISSN: None     Source Type: Journal    
DOI: 10.1109/tce.2006.1605057     Document Type: Article

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