BEOL process integration with Cu/SiCOH (k=2.8) low-k interconnects at 65nm groundrules

Advanced Metallization Conference (AMC)

Volumn , Issue , 2006, Pages 61-71

  Lane, S ^a   Fukasawa, M ^a   Angyal, M ^a   Chanda, K ^a   Chen, F ^a   Christiansen, C ^a   Fitzsimmons, J ^a   Gill, J ^a   Ida, K ^a   Inoue, K ^a   Kumar, K ^a   Li, B ^a   McLaughlin, P ^a   Melville, I ^a   Minami, M ^a   Nguyen, S ^a   Penny, C ^a   Sakamoto, A ^a   Shimooka, Y ^a   Ono, M ^a   McHerron, D ^a   Nogami, T ^a   Ivers, T ^a   more..

^a IBM RESEARCH   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CHIP-TO-PACKAGE (CPI); DIRECT-CMP PROCESSING; SICOH MATERIAL; 3D MODELING; INTERCONNECT TECHNOLOGY; STRIP PROCESSES;

ETCHING; LARGE SCALE SYSTEMS; MATHEMATICAL MODELS; RELIABILITY; SILICON WAFERS; THIN FILMS; ELECTRIC PROPERTIES; OPTIMIZATION;

COPPER;

EID: 33644941753     PISSN: 15401766     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (7)

1. D. Edelstein et al., Proc. IEEE IITC 2004, p. 214.
2. A. Grill et al., Proc. IEEE IITC 2004, p. 54.
3. M. Angyal et al., AMC 2005 to be published
4. K. Ida et al., AMC 2005 to be published
5. T. Tokuyama et al., "Chou-Bisaikakou-Gijyutu" (in Japanese), p. 222.
6. M. Fukasawa et al., Proc. International Microprocesses and Nanotechnology Conference 1997, p. 186.
7. T. Nogami et. al. MIC-CMP 2004 Keynote speech