A thermal, mechanical, and electrical study of voiding in the solder die-attach of power MOSFETs

IEEE Transactions on Components and Packaging Technologies

Volumn 29, Issue 1, 2006, Pages 127-136

  Katsis, Dimosthenis C ^a   van Wyk, Jacobus Daniel ^b  

^a U S ARMY RESEARCH LABORATORY   (United States)

^b State University   (United States)

Author keywords

Die attach; Hot spots; Power electronics; Thermal degradation

Indexed keywords

ELECTRIC PROPERTIES; FINITE ELEMENT METHOD; MATHEMATICAL MODELS; MECHANICAL PROPERTIES; POWER ELECTRONICS; PYROLYSIS; SOLDERING; TEMPERATURE;

DIE-ATTACH DEFECTS; POWER SEMICONDUCTOR DEVICES; SEMICONDUCTOR PACKAGE; SILICON DIE; THERMAL IMPEDANCE; THERMAL MODELING;

MOSFET DEVICES;

EID: 33644806969     PISSN: 15213331     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAPT.2005.853301     Document Type: Article

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