A 400 Gbps backplane switch with 10 Gbps/port optical I/O interfaces

Proceedings of SPIE - The International Society for Optical Engineering

Volumn 6014, Issue , 2005, Pages

  Hatakeyama, Ichiro ^a   Miyoshi, Kazunori ^a   Sasaki, Jun'ichi ^a   Yamamoto, Keisuke ^a   Kurihara, Mitsuru ^a   Watanabe, Takanori ^a   Ushioda, Jun ^a   Hashimoto, Yoichi ^a   Kuribayashi, Ryosuke ^a   Kurata, Kazuhiko ^a  

^a NEC CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; LSI CIRCUITS; OPTICAL INTERCONNECTS; SILICON COMPOUNDS; WAVELENGTH DIVISION MULTIPLEXING;

BACKPLANE SWITCH;

OPTICAL COMMUNICATION;

EID: 33644759447     PISSN: 0277786X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1117/12.632379     Document Type: Conference Paper

References (4)

1. http://grouper.ieee.org/groups/802/3/bladesg/index.html
2. M. Fukaishi, K. Nakamura, H. Heiuchi, Y. Hirota, Y. Nakazawa, H. Ikeno, H. Hayama, and M. Yotsuyanagi, "A 20-Gb/s CMOS Multi-Channel Transmitter and Receiver Chip Set for Ultra-High-Resolution Digital Displays," IEEE J. Solid-State Circuits, Vol. 35, No. 11, pp. 1611-1618, Nov. 2000.
3. T. Yoshikawa, I. Hatakeyama, K. Miyoshi, K. Kurata, J. Sasaki, N. Kami, T. Sugimoto, M. Fukaishi, K. Nakamura, K. Tanaka, H. Nishi, and T. Kudoh, "Optical-Interconnection as an IP Macro of a CMOS Library," Proc. of Hot Interconnects 9, pp. 31-35, Stanford, USA, Aug. 2001.
4. I. Hatakeyama, T. Yoshikawa, K. Miyoshi, K. Kurata, K. Tanaka, M. Fukaishi, K. Nakamura, K. Nakamura, S. Dohmae, and H. Tanaka, "A 16×16 Crosspoint Switch with 3.125-Gbit/s/port Optical I/O Interfaces based on OIP (Optical-interconnection as IP of a CMOS Library) Design Concept," Photonics in Switching 2002, PS.WeA3, pp. 10-112, Jul. 2002.