An ultra low-power adiabatic adder embedded in a standard 0.13μm CMOS environment

European Solid-State Circuits Conference

Volumn , Issue , 2003, Pages 599-602

  Amirante, Ettore ^a   Fischer, Jürgen ^a   Lang, Marhs ^a   Bargagli Stoffi, Agnese ^a   Berthold, Jörg ^b   Heer, Christoph ^b   Schmitt Landsiedel, Dons ^a  

^a TECHNICAL UNIVERSITY OF MUNICH   (Germany)

^b INFINEON TECHNOLOGIES AG   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

ADIABATIC CIRCUITS; ADIABATIC LOGIC; ADIABATIC SYSTEMS; DESIGN COMPLEXITY; INTERFACE CIRCUITS; LOW POWER APPLICATION; POWER CLOCK GENERATOR; RIPPLE CARRY ADDERS;

ADDERS; CMOS INTEGRATED CIRCUITS; ENERGY EFFICIENCY;

MICROPROCESSOR CHIPS;

EID: 33644648726     PISSN: 19308833     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ESSCIRC.2003.1257206     Document Type: Conference Paper

References (5)

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2. A. Vetuli, S. Di Pascoli and L. M. Reyneri: "Positive feedback in adia-batic logic". Electronics Letters, Vol. 32, No. 20, Sep. 1996, pp. 1867ff.
3. A. Blotti, S. Di Pascoli and R. Saletti: "Simple model for positive-feedback adiabatic logic power consumption estimation". Electronics Letters, Vol. 36, No. 2, Jan. 2000, pp. 116-118.
4. E. Amirante, A. Bargagli-Stofri, J. Fischer, G. lannaccone and D. Schmitt-Landsiedel: "Adiabatic 4-bit Adders. Comparison of Per-formance and Robustness against Technology Parameter Variations". Proc. 45th IEEE Intern. Midwest Symposium on Circuits and Systems, MWSCAS'02, Tulsa, OK, USA, Vol. Ill, Aug. 2002, pp. 644-647.
5. A. Bargagli-Stoffi, G. lannaccone, S. Di Pascoli, E. Amirante and D. Schmitt-Landsiedd: "Four-phase power clock generator for adia-batic logic circuits". Electronics Letters, Vol, 38, No. 14, July 2002, pp. 689-690.