A Miller divider based clock generator for MBOA-UWB application

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn 2005, Issue , 2005, Pages 34-37

  Lee, Tai Cheng ^a   Huang, Yen Chuang ^a  

^a NATIONAL TAIWAN UNIVERSITY   (Taiwan)

Author keywords

Clock generator; Miller divider; UWB

Indexed keywords

BROADBAND NETWORKS; CLOSED LOOP CONTROL SYSTEMS; FREQUENCY DIVIDING CIRCUITS; ORTHOGONAL FREQUENCY DIVISION MULTIPLEXING; TRANSISTORS;

CLOCK GENERATORS; CLOSED LOOP OPERATION; MILLER DIVIDERS; UWB;

SIGNAL GENERATORS;

EID: 33644642348     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSIC.2005.1469327     Document Type: Conference Paper

References (3)

1. R. L. Miller, "Fractional-frequency Generators Utilizing Regenerative Modulation," Proc. Inst. Radio Eng, vol. 27, pp. 446-456, July 1939.
2. J. Lee and B. Razavi, "A 40-GHz Frequency Divider in 0.18-μ m CMOS Technology," IEEE J. of Solid-State Circuits, vol. 39, pp. 594-601, April 2004.
3. T. Lee and Y. Huang, "An Optimization Technique for RF Buffers with Active Inductors," to be appeared at ISCAS 2005.