Modeling of gate line delay in very large active matrix liquid crystal displays

IEEE Transactions on Electron Devices

Volumn 45, Issue 1, 1998, Pages 343-345

  Zhang, Qing ^a   Shen, D S ^a   Gleskova, H ^a   Wagner, S ^a  

^a UNIVERSITY OF ALABAMA IN HUNTSVILLE   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 33644610274     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/16.658856     Document Type: Article

References (4)

1. W. E. Howard, "Limitations and prospects of a-Si:H TFT's," J. SID, vol. 3/3, p. 27, 1995.
2. H. Gleskova, S. Wagner, Q. Zhang, and D. S. Shen, "Via hole technology for thin film transistor circuits," IEEE Electron Device Lett., vol. 18, pp. 523-525, 1997.
3. R. L. Wisnieff, "Line delay and capacitive crosstalk effects in TFT/LCD's," in Proc. SID, vol. 29, no. 2, p. 173-178, 1988.
4. J. M. Rabaey, Digital Integrated Circuits. Englewood Cliffs, NJ: Prentice-Hall, 1996.