Efficient placement and routing in grid-based networks

Proceedings of the ACM Symposium on Applied Computing

Volumn 1, Issue , 2005, Pages 899-900

  Jafari, Roozbeh ^a   Dabiri, Foad ^a   Choi, Bo Kyung ^a   Sarrafzadeh, Majid ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

Fault Tolerance; Placement; Routing; Sensor Networks

Indexed keywords

GRID-BASED NETWORKS; PLACEMENT; ROUTING; SENSOR NETWORKS;

ACTUATORS; DISTRIBUTED COMPUTER SYSTEMS; OPTIMIZATION; PROBABILITY; PROBLEM SOLVING; ROUTERS; SENSORS;

COMPUTER NETWORKS;

EID: 33644515274     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1066677.1066882     Document Type: Conference Paper

References (4)

1. Sarrafzadeh, M. and Wong, M. An Introduction to VLSI Physical Design. McGraw-Hill, 1996.
2. Sherwani, N.A. Algorithms for VLSI Physical Design Automation. Kluwer Academic Publishers, 1993.
3. Sun, W.J., and Sechen, C. Efficient and Effective Placement for Very Large Circuits. IEEE Transactions on Computer-Aided Design of Integrated Circuits, 14(3):349-359, March 1995.
4. Dunlop, A.E., and Kernighan, B.W. A Procedure for Placement of Standard Cell VLSI Circuits. IEEE Transactions on Computer-Aided Design of Integrated Circuits, 4(1):92-98, January 1985.