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Volumn 51, Issue 3 I, 2004, Pages 334-339

Upgrade of the level-0 trigger system for BNL-E949

(22)  Yoshioka, T a   Nomachi, M b   Artamanov, A c   Bhuyan, B d,e,f   Frank, J S d   Fujiwara, T g   Higa, K b   Kettell, S H d   Komatsubara, T K a   Konaka, A h   Kozjevnikov, A c   Kushnirenko, A c,i   Muramatsu, N j   Nakano, T b   Nomura, T g   Petrenko, S c   Poutissou, R h   Redlinger, G d   Sekiguchi, T a   Shinkawa, T k   more..

h TRIUMF   (Canada)

Author keywords

Complex programmable logic device (CPLD); Field programmable gate array (FPGA); Mean timer; Trigger

Indexed keywords

FIELD PROGRAMMABLE GATE ARRAYS; LOGIC DEVICES; MICROPROCESSOR CHIPS; ONLINE SYSTEMS; PHOTONS; SCINTILLATION; SENSITIVITY ANALYSIS; SYNCHROTRONS;

EID: 3342992710     PISSN: 00189499     EISSN: None     Source Type: Journal    
DOI: 10.1109/TNS.2004.828867     Document Type: Conference Paper
Times cited : (7)

References (11)
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.