Trace-driven memory simulation: A survey

ACM Computing Surveys

Volumn 29, Issue 2, 1997, Pages

  Uhlig, Richard A ^a   Mudge, Trevor N ^b  

^a INTEL CORPORATION   (United States)

^b UNIVERSITY OF MICHIGAN   (United States)

Author keywords

Caches; Memory management; Memory simulation; TLBs; Trace driven simulation

Indexed keywords

EID: 3342931131     PISSN: 03600300     EISSN: None     Source Type: Journal    
DOI: 10.1145/254180.254184     Document Type: Review

References (118)

1. AGARWAL, A. 1989. Analysis of cache performance for operating systems and multiprogramming. Ph.D. Dissertation, Stanford.
2. AGARWAL, A. AND HUFFMAN, M. 1990. Blocking: Exploiting spatial locality for trace compaction. In Proceedings of the 1990 SIGMETRICS Conference on Measurement and Modeling of Computer Systems (Boulder, CO), ACM, New York, 48-57.
3. AGARWAL, A., HENNESSY, J., AND HOROWITZ, M. 1988. Cache performance of operating system and multiprogramming workloads. ACM Trans. Comput. Syst. 6, 4, 393-431.
4. AGARWAL, A., HOROWITZ, M., AND HENNESSY, J. 1989. An analytical cache model. ACM Trans. Comput. Syst. 7, 2, 184-215.
5. AGARWAL, A., SITES, R. L., AND HOROWITZ, M. 1986. ATUM: A new technique for capturing address traces using microcode. In Proceedings of the 13th International Symposium on Computer Architecture (Tokyo, Japan), IEEE, New York, 119-127.
6. ALEXANDER, C. A., KESHLEAR, W. M., AND BRIGGS, F. 1985. Translation buffer performance in a UNIX environment. Comput. Arch. News 13, 5, 2-14.
7. ALEXANDER, C., KESHLEAR, W., COOPER, F., AND BRIGGS, F. 1986. Cache memory performance in a UNIX environment. Comput. Arch. News 14, 14-70.
8. AMD 1991. Am29050 Microprocessor User's Manual. Advanced Micro Devices, Inc., Sunnyvale, CA.
9. AMD 1993. Am486 DX/DX2 Microprocessor Hardware Reference Manual. Advanced Micro Devices, Inc., Sunnyvale, CA.
10. BAKER, M. 1995. Cluster computing review. Northeast Parallel Architectures Center (NPAC) Techn. Rep. SCCS-748, Nov.
11. BECKER, J. AND PARK, A. 1993. An analysis of the information content of address and data reference streams. In Proceedings of the 1993 SIGMETRICS Conference on the Measurement and Modeling of Computer Systems (Santa Clara, CA), 262-263.
12. BEDICHEK, R. 1994. The meerkat multicomputer: Tradeoffs in multicomputer architecture. Ph.D. Dissertation, University of Washington Department of Computer Science Techn. Rep. 94-06-06, Aug.
13. BEDICHEK, R. 1995. Talisman: Fast and accurate multicomputer simulation. In Proceedings of the 1995 SIGMETRICS Conference on Measurement and Modeling of Computer Systems, 14-24.
14. BIOMATION 1991. Biomation CLAS 4000 application note 4032. Biomation, Cupertino, CA.
15. BORG, A., KESSLER, R., LAZANA, G., AND WALL, D. 1989. Long address traces from RISC machines: Generation and analysis. DEC Western Research Lab Tech. Rep. 89/14.
16. BORG, A., KESSLER, R., AND WALL, D. 1990. Generation and analysis of very long address traces. In Proceedings of the 17th Annual International Symposium on Computer Architecture, IEEE, New York.
17. CHEN, B. 1993. Software methods for system address tracing. In Proceedings of the Fourth Workshop on Workstation Operating Systems (Napa, CA).
18. CHEN, B. 1994. Memory behavior of an X11 window system. In Proceedings of the USENIX Winter 1994 Technical Conference.
19. CHEN, B. AND BERSHAD, B. 1993. The impact of operating system structure on memory system performance. In Proceedings of the 14th Symposium on Operating System Principles.
20. CLARK, D. W., BANNON, P. J., AND KELLER, J. B. 1985. Measuring VAX 8800 performance with a histogram hardware monitor. In Proceedings of the 15th Annual International Symposium on Computer Architecture (Honolulu, Hawaii), IEEE, New York, 176-185.
21. CMELIK, R. AND KEPPEL, D. 1993. Shade: A fast instruction-set simulator for execution profiling. University of Washington Tech. Rep. UWCSE 93-06-06.
22. CMELIK, B. AND KEPPEL, D. 1994. Shade: A fast instruction-set simulator for execution profiling. In Proceedings of the 1994 SIGMETRICS Conference on Measurement and Modeling of Computer Systems (Nashville, TN), ACM, New York, 128-137.
23. COVINGTON, R. C., MADALA, S., MEHTA, V., JUMP, J. R., AND SINCLAIR, J. B. 1988. The Rice parallel processing testbed. In Proceedings of the 1988 SIGMETRICS Conference on Measurement and Modeling of Computer Systems, ACM, New York, 4-11.
24. CVETANOVIC, Z. AND BHANDARKAR, D. 1994. Characterization of Alpha AXP performance using TP and SPEC Workloads. In Proceedings of the 21st Annual International Symposium on Computer Architecture (Chicago, IL), IEEE, New York.
25. DAVIES, P., LACROUTE, P., HEINLEIN, J., AND HOROWITZ, M. 1994. Mable: A technique for efficient machine simulation. Stanford University Tech. Rep. CSL-TR-94-636, Oct.
26. DAVIS, H., GOLDSCHMIDT, S., AND HENNESSY, J. 1991. Multiprocessor simulation and tracing using Tango. In Proceedings of the 1991 International Conference on Parallel Processing, 99-107.
27. DIGITAL 1986. VAX Architecture Handbook. Digital Equipment Corporation, Bedford, MA.
28. DIGITAL 1992. Alpha Architecture Handbook. Digital Equipment Corporation, Bedford, MA.
29. EGGERS, S., KEPPEL, D., KOLDINGER, E., AND LEVY, H. 1990. Techniques for efficient inline tracing on a shared-memory multiprocessor. In Proceedings of the 1990 SIGMETRICS Conference on Measurement and Modeling of Computer Systems (Boulder, CO), 37-47.
30. EMER, J. AND CLARK, D. A. 1984. A characterization of processor performance in the VAX-11/780. In Proceedings of the 11th Annual Symposium on Computer Architecture (Ann Arbor, MI), IEEE, New York, 301-309.
31. EUSTACE, A. AND SRIVASTAVA, A. 1995. ATOM: A flexible interface for building high performance program analysis tools. In Proceedings of the USENIX Winter 1995 Technical Conference on UNIX and Advanced Computing Systems (New Orleans, LA), Jan., 303-314.
32. FLANAGAN, J. K., NELSON, B. E., ARCHIBALD, J. K., AND GRIMSRUD, K. 1992. BACH: BYU address collection hardware, the collection of complete traces. In Proceedings of the Sixth International Conference on Modelling Techniques and Tools for Computer Performance Evaluation, 128-137.
33. FLANAGAN, J. K. 1994. Personal communication.
34. FUENTES, C. 1993. Hardware support for operating systems. University of Michigan Unpublished report.
35. GEE, J., HILL, M., PNEVMATIKATOS, D., AND SMITH, A. J. 1993. Cache performance of the SPEC92 benchmark suite. IEEE Micro (Aug.), 17-27.
36. GOLDSCHMIDT, S. AND HENNESSY, J. 1992. The accuracy of trace-driven simulation of multiprocessors. Stanford University Computer Systems Laboratory Tech. Rep. CSL-TR-92-546, Sept.
37. GOLDSCHMIDT, S. AND HENNESSY, J. 1993. The accuracy of trace-driven simulation of multiprocessors. In Proceedings of the 1993 ACM SIGMETRICS Conference on Measurement and Modeling of Computer Systems (May), 146-157.
38. GRIMSRUD, K. 1993. Address translation of BACH i486 traces. Brigham Young University Tech. Rep.
39. HAMMERSTROM, D. AND DAVIDSON, E. 1977. Information content of CPU memory referencing behavior. In Proceedings of the Fourth International Symposium on Computer Architecture, 184-192.
40. HAPPEL, L. P. AND JAYASUMANA, A. P. 1992. Performance of a. RISC machine with two-level caches. IEEE Proceedings-E 139, 3, 221-229.
41. HENNESSY, J. L. AND PATTERSON, D. A. 1996. Computer Architecture, A Quantitative Approach. 2nd ed. Morgan Kaufmann, San Mateo, CA.
42. HEWLETT-PACKARD 1990. PA-RISC 1.1 Architecture and Instruction Set Reference Manual. Hewlett-Packard, Inc.
43. HEWLETT-PACKARD 1991. Test and Measurement Catalog. Marketing Communications, Santa Clara, CA.
44. HILL, M. 1987. Aspects of cache memory and instruction buffer performance. Ph.D. Dissertation, The University of California at Berkeley.
45. HILL, M. AND SMITH, A. 1989. Evaluating associativity in CPU caches. IEEE Trans. Comput. 38, 12, 1612-1630.
46. HODGES, J. L. AND LEHMANN, E. L. 1964. Basic Concepts of Probability and Statistics. Holden-Day, Inc., San Francisco, CA.
47. HOLLIDAY, M. AND ELLIS, C. 1990. Accuracy of memory reference traces of parallel computations in trace-driven simulation. Department of Computer Science, Duke University, Durham, NC. Tech. Rep. CS-1990-8.
48. HOLLIDAY, M. 1991. Techniques for cache and memory simulation using address reference traces. Int. J. Comput. Simul. 1, 129-151.
49. IBM 1990. IBM RISC System/6000 Technology. IBM, Austin, TX.
50. INTEL 1990. i860 64-bit Microprocessors Programmer's Manual. Intel Corporation, Santa Clara, CA.
51. JOUPPI, N. 1990. Improving direct-mapped cache performance by the addition of a small fully associative cache and prefetch buffers. In Proceedings of the 17th Annual International Symposium on Computer Architecture (Seattle, WA), IEEE, New York, 364-373.
52. KANE, G. AND HEINRICH, J. 1992. MIPS RISC Architecture. Prentice-Hall, Englewood Cliffs, NJ.
53. KAELI, D. 1991. Issues in trace-driven simulation. In Proceedings of the 22nd Annual Pittsburgh Modeling and Simulation Conference, Vol. 22, Part 5, May, 2533-2540.
54. KESSLER, R. 1991. Analysis of multi-megabyte secondary CPU cache memories. Ph.D. Dissertation, University of Wisconsin-Madison.
55. LACY, F. 1988. An address trace generator for trace-driven simulation of shared memory multiprocessors. University of California at Berkeley. Tech. Rep. UCB/CSD 88/407.
56. LAHA, S., PATEL, J., AND IYER, R. 1988. Accurate low-cost methods for performance evaluation of cache memory systems. IEEE Trans. Comput. 37, 11, 1325-1336.
57. LARUS, J. R. 1990. Abstract execution: A technique for efficiently tracing programs. Softw. Pract. Exper. 20, 12 (Dec.) 1241-1258.
58. LARUS, J. 1991. SPIM S20: A MIPS R2000 simulator. University of Wisconsin-Madison Tech. Rep., Revision 9.
59. LARUS, J. R. 1993. Efficient program tracing. IEEE Computer (May), 52-60.
60. LEBECK, A. AND WOOD, D. 1994. Fast-Cache: A new abstraction for memory-system simulation. University of Wisconsin-Madison Tech. Rep. 1211.
61. LEBECK, A. AND WOOD, D. 1995. Active memory: A new abstraction for memory-system simulation. In Proceedings of the 1995 SIGMETRICS Conference on the Measurement and Modeling of Computer Systems (May), 220-230.
62. LEE, C.-C. 1997. A case study of a hardware-managed TLB in a multi-tasking environment. University of Michigan Tech. Rep.
63. MACWEEK STAFF 1994. Apple holds up 603 for cache. MacWeek 8, 21 (May 24), 1, 100.
64. MAGNUSSON, P. A. 1993. A design for efficient simulation of a multiprocessor. In Proceedings of the 1993 Western Simulation Multiconference on International Workshop on Modeling, Analysis and Simulation of Computer and Telecommunications Systems (MASCOTS-93) (La Jolla, CA) 69-78.
65. MARTONOSI, M. 1994. Analyzing and tuning memory performance in sequential and parallel programs. Ph.D. Dissertation, Stanford University.
66. MARTONOSI, M., GUPTA, A., AND ANDERSON, T. 1992. MemSpy: Analyzing memory system bottlenecks in programs. In Proceedings of the 1992 SIGMETRICS Conference on the Measurement and Modeling of Computer Systems, ACM, New York.
67. MARTONOSI, M., GUPTA, A., AND ANDERSON, T. 1993. Effectiveness of trace sampling for performance debugging tools. In Proceedings of the 1993 SIGMETRICS Conference on the Measurement and Modeling of Computer Systems (Santa Clara, CA), ACM, New York, 248-259.
68. MATTSON, R. L., GECSEI, J., SLUTZ, D. R., AND TRAIGER, I. L. 1970. Evaluation techniques for storage hierarchies. IBM Syst. J. 9, 2, 78-117.
69. MAY, C. 1987. Mimic: A fast S/370 simulator. In Proceedings of the ACM SIGPLAN 1987 Symposium on Interpreters and Interpretive Techniques (St. Paul, MN), ACM, New York, 1-13.
70. MAYNARD, A. M., DONNELLY, C., AND OLSZEWSKI, B. 1994. Contrasting characteristics and cache performance of technical and multi-user commercial workloads. In Proceedings of the Sixth International Conference on Architectural Support for Programming Languages and Operating Systems (San Jose, CA), ACM, New York, 145-156.
71. MIPS. 1988. RISCompiler Languages Programmer's Guide. MIPS.
72. MOGUL, J. C. AND BORG, A. 1991. The effect of context switches on cache performance. In Proceedings of the Fourth International Conference on Architectural Support for Programming Languages and Operating Systems (Santa Clara, CA), ACM, New York, 75-84.
73. MOTOROLA 1990. MC88100 RISC Microprocessor User's Manual. Prentice-Hall, Englewood Cliffs, NJ.
74. MOTOROLA 1993. Power PC 601 RISC Microprocessor User's Manual. Motorola, Inc.
75. NAGLE, D., UHLIG, R., AND MUDGE, T. 1992. Monster: A tool for analyzing the interaction between operating systems and computer architectures. University of Michigan Tech. Rep. CSE-TR-147-92.
76. NAGLE, D., UHLIG, R., STANLEY, T., SECHREST, S., MUDGE, T., AND BROWN, R. 1993. Design tradeoffs for software-managed TLBs. In Proceedings of the 20th Annual International Symposium on Computer Architecture (San Diego, CA), IEEE, 27-38.
77. NAGLE, D., UHLIG, R., MUDGE, T., AND SECHREST, S. 1994. Optimal allocation of on-chip memory for multiple-API operating systems. In Proceedings of the 21st International Symposium on Computer Architecture (Chicago, IL).
78. PIERCE, J. AND MUDGE, T. 1994a. IDtrace - A tracing tool for i486 simulation. University of Michigan Tech. Rep. CSE-TR-203-94.
79. PIERCE, J. AND MUDGE, T. 1994b. IDtrace - A tracing tool for i486 simulation (extended abstract). In Proceedings of the International Workshop on Modeling, Analysis and Simulation of Computer and Telecommunications Systems (MASCOTS), 419-420.
80. PIERCE, J., SMITH, M. D., AND MUDGE, T. 1995. Instrumentation tools. In Fast Simulation of Computer Architectures, (T. M. Conte and C. E. Gimarc, Eds.), Kluwer Academic Publishers, Boston, MA (to appear).
81. PLESZKUN, A. 1994. Techniques for compressing program address traces. Tech. Rep., Department of Electrical and Computer Engineering, University of Colorado-Boulder.
82. PRIEVE, B. G. 1974. A Page Partition Replacement Algorithm. University of California at Berkeley.
83. PUZAK, T. 1985. Analysis of cache replacement algorithms. Ph.D. Dissertation, University of Massachusetts.
84. REINHARDT, S., HILL, M., LARUS, J., LEBECK, A., LEWIS, J., AND WOOD, D. 1993. The Wisconsin Wind Tunnel: Virtual prototyping of parallel computers. In Proceedings of the 1993 SIGMETRICS International Conference on Measurement and Modeling of Computer Systems (Santa Clara, CA), ACM, New York, 48-60.
85. REINHARDT, S., PFILE, R., AND WOOD, D. 1996. Decoupled hardware support for distributed shared memory. In Proceedings of the 23rd Annual International Symposium on Computer Architecture (to appear).
86. ROMER, T., LEE, D., VOELKER, G., WOLMAN, A., WONG, W., BAER, J., BERSHAD, B., AND LEVY, H. 1996. The structure and performance of interpreters. In Proceedings of the Seventh International Conference on Architectural Support for Programming Languages and Operating Systems (Cambridge, MA, Oct.), (to appear).
87. ROSENBLUM, M., HERROD, S., WITCHEL, E., AND GUPTA, A. 1995. Complete computer simulation: The SimOS approach. IEEE Parallel Distrib. Technol. (Fall).
88. SAMPLES, A. 1989. Mache: No-loss trace compaction. In Proceedings of 1989 SIGMETRICS Conference on Measurement and Modeling of Computer Systems, ACM, New York, 89-97.
89. SITES, R. L. AND AGARWAL, A. 1988. Multiprocessor cache analysis with ATUM. In Proceedings of the 15th Annual International Symposium on Computer Architecture (Honolulu), IEEE, New York, 186-195.
90. SITES, R., CHERNOFF, A., KIRK, M., MARKS, M., AND ROBINSON, S. 1992. Binary translation. Digital Tech. J. 4, 4, 137-152.
91. SMITH, A. J. 1977. Two methods for the efficient analysis of memory address trace data. IEEE Trans. Softw. Eng. SE-3, 1, 94-101.
92. SMITH, A. J. 1982. Cache memories. Comput. Surv. 14, 3, 473-530.
93. SMITH, A. 1986. Bibliography and readings on CPU cache memories and related topics. Comput. Arch. News 14, 22-42.
94. SMITH, M. D. 1991. Tracing with pixie. Tech. Rep., Stanford University, Stanford, CA.
95. SRIVASTAVA, A. AND EUSTACE, A. 1994. ATOM: A system for building customized program analysis tools. In Proceedings of the SIGPLAN '94 Conference on Programming Language Design and Implementation (June), 196-205.
96. STEPHENS, C., COGSWELL, B., HEINLEIN, J., PALMER, G., AND SHEN, J. 1991. Instruction level profiling and evaluation of the IBM RS/6000. In Proceedings of the 18th Annual International Symposium on Computer Architecture (Toronto, Canada), ACM, New York, 180-189.
97. STONE, H. 1993. High-Performance Computer Architecture. Addison-Wesley, Reading, MA.
98. STUNKEL, C. AND FUCHS, W. 1989. TRAPEDS: Producing traces for multicomputers via execution-driven simulation. In Proceedings of the 1989 SIGMETRICS Conference on Measurement and Modeling of Computer Systems (Berkeley, CA), ACM, New York, 70-78.
99. STUNKEL, C., JANSSENS, B., AND FUCHS, W. K. 1991. Collecting address traces from parallel Computers. In Proceedings of the 24th Annual Hawaii International Conference on System Sciences (Hawaii), 373-383.
100. SUGUMAR, R. 1993. Multi-configuration simulation algorithms for the evaluation of computer designs. Ph.D. Dissertation, University of Michigan.
101. TALLURI, M. AND HILL, M. 1994. Surpassing the TLB performance of superpages with less operating system support. In Proceedings of the Sixth International Conference on Architectural Support for Programming Languages and Operating Systems (San Jose, CA), ACM, New York.
102. TEKTRONIX. 1994. Test and Measurement Product Catalog. Wilsonville, OR.
103. THEKKATH, C. AND LEVY, H. 1994. Hardware and software support for efficient exception handling. In Proceedings of the Sixth International Conference on Architectural Support for Programming Languages and Operating Systems (San Jose, CA), ACM Press, New York, 110-119.
104. THOMPSON, J. AND SMITH, A. 1989. Efficient (stack) algorithms for analysis of write-back and sector memories. ACM Trans. Comput. Syst. 7, 1, 78-116.
105. TORRELLAS, J., GUPTA, A., AND HENNESSY, J. 1992. Characterizing the caching and synchronization performance of multiprocessor operating system. In Proceedings of the Fifth International Conference on Architectural Support for Programming Languages and Operating Systems (Boston, MA), 162-174.
106. UHLIG, R., NAGLE, D., MUDGE, T., AND SECHREST, S. 1994. Trap-driven simulation with Tapeworm II. In Proceedings of the Sixth International Conference on Architectural Support for Programming Languages and Operating Systems (San Jose, CA), ACM Press (SIGARCH), New York, 132-144.
107. UHLIG, R., NAGLE, D., MUDGE, T., SECHREST, S., AND EMER, J. 1995. Instruction fetching: Coping with code bloat. In Proceedings of the 22nd International Symposium on Computer Architecture (Santa Margherita Ligure, Italy, June) (to appear).
108. UPTON, M. D. 1994. Architectural trade-offs in a latency tolerant gallium arsenide microprocessor. Ph.D. Dissertation, The University of Michigan.
109. VEENSTRA, J. AND FOWLER, R. 1994. MINT: A front end for efficient simulation of shared-memory multiprocessors. In Proceedings of the Second International Workshop on Modeling, Analysis, and Simulation of Computer and Telecommunications Systems (MASCOTS), 201-207.
110. WALL, D. 1989. Link-time code modification. DEC Western Research Lab Tech. Rep. 89/17.
111. WALL, D. 1992. Systems for late code modification. DEC Western Research Lab. Tech. Rep. 92/3.
112. WANG, W.-H. AND BAER, J.-L. 1990. Efficient trace-driven simulation methods for cache performance analysis. In Proceedings of the 1990 SIGMETRICS Conference on Measurement and Modeling of Computer Systems (Boulder, CO), ACM, New York, 27-36.
113. WIECEK, C. A. 1982. A case study of VAX-11 instruction set usage for compiler execution. In Proceedings of Architectural Support for Programming Languages and Operating Systems, ACM Press, New York, 177-184.
114. WILKES, M. 1969. The growth of interest in microprogramming: A literature survey. Comput. Surv. 1, 3 (Sept.), 139-145.
115. WINSOR, D. 1989. Bus and cache memory organizations for multi-processors. Ph.D. Dissertation. University of Michigan.
116. WITCHEL, E. AND ROSENBLUM, M. 1996. Embra: Fast and flexible machine simulation. In Proceedings of the 1996 SIGMETRICS Conference on Measurement and Modeling of Computer Systems (Philadelphia, May).
117. WOOD, D., HILL, M., AND KESSLER, R. 1991. A model for estimating trace-sampled miss ratios. In Proceedings of the 1991 SIGMETRICS Conference on Measurement and Modeling of Computer Systems, 79-89.
118. ZIV, J. AND LEMPEL, A. 1976. A universal algorithm for sequential data compression. IEEE Trans. Inf. Theory 23, 75-81.