A Low-Power CMOS Analog Multiplier

IEEE Transactions on Circuits and Systems II: Express Briefs

Volumn 53, Issue 2, 2006, Pages 100-104

  Chen, Chunhong ^a   Li, Zheng ^a  

^a UNIVERSITY OF WINDSOR   (Canada)

Author keywords

Analog integrated circuits; analog multipliers; CMOS; low power design

Indexed keywords

COMPUTER SIMULATION; ELECTRON MULTIPLIERS; INTEGRATED CIRCUIT TESTING; LINEAR INTEGRATED CIRCUITS;

ANALOG INTEGRATED CIRCUITS; ANALOG MULTIPLIERS; CHIP TESTING; LOW POWER CONSUMPTION; LOW-POWER DESIGN;

CMOS INTEGRATED CIRCUITS;

EID: 33144479108     PISSN: 15497747     EISSN: 15583791     Source Type: Journal    
DOI: 10.1109/TCSII.2005.857089     Document Type: Article

References (14)

1. K. Bult and H. Wallinga, “A four-quadrant analog multiplier,” IEEE J. Solid-State Circuits, vol. SC-21, no. 3, pp. 430–435, Jun. 1986.
2. O. Changyue, C. Peng, and X. Yizhong, “Study of switched capacitor multiplier,” in Proc. Int. Conf. Circuits Syst, Jun. 1991, pp. 234–237.
3. Z. Wang, “A four-transistor four-quadrant analog multiplier using MOS transistors operating in the saturation region,” IEEE Trans. Instrum. Meas., vol. 42, no. 1, pp. 75–77, Feb. 1993.
4. H. R. Mehrvarz and C. Y. Kwok, “A large-input-dynamic-range multi-input floating gate MOS four-quadrant analog multiplier,” in Proc. IEEE Int. Solid-State Circuits Conf., Feb. 1995, pp. 60–61.
5. S. Liu and C. Chang, “CMOS subthreshold four quadrant multiplier based on unbalanced source coupled pairs,” Int. J. Electron., vol. 78, pp. 327–332, Feb. 1995.
6. B. Maundy and P. Aronhime, “Useful multipliers for low-voltage applications,” in Proc. IEEE Int. Symp. Circuits Syst., vol. 1, May 2002, pp. 26–29.
7. G. Han and E. Sanchez-Sinencio, “CMOS transconductance multipliers: A tutorial,” IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 45, no. 12, pp. 1550–1563, Dec. 1998.
8. U. Gatti, F. Maloberti, and G. Torelli, “CMOS triode-transistor transconductor for high-frequency continuous-time filters,” Proc. IEE Circuits, Devices, Syst., vol. 141, no. 6, pp. 462-468, Dec. 1994.
9. S. Liu and Y. Hwang, “CMOC four-quadrant multiplier using bias feedback techniques,” IEEE J. Solid-State Circuits, vol. 29, pp. 750–752, Jun. 1994.
10. S. I. Liu, “Low voltage CMOS four-quadrant multiplier,” Electron. Lett., vol. 30, pp. 2125–2126, Dec. 1994.
11. B. Gibert, “A precision four-quadrant multiplier with subnanosecond response,” IEEE J. Solid-State Circuits, vol. SC-3, no. 6, pp. 353–365, Dec. 1968.
12. D. C. Soo and R. G. Meyer, “A four-quadrant nMOS analog multiplier,” IEEE J. Solid-State Circuits, vol. SC-17, no. 6, pp. 1174–1178, Dec. 1982.
13. J. N. Babanezhad and G. C. Temes, “A 20-V four-quadrant CMOS analog multiplier,” IEEE J. Solid-State Circuits, vol. SC-20, no. 6, pp. 1158–1168, Dec. 1985.
14. B. Razavi, Design of Analog CMOS Integrated Circuits. New York: McGraw-Hill, 2001.