A VLSI architecture for high performance CABAC encoding

Proceedings of SPIE - The International Society for Optical Engineering

Volumn 5960, Issue 3, 2005, Pages 1444-1454

  Shojania, Hassan ^a   Sudharsanan, Subramania ^a  

^a QUEEN S UNIVERSITY   (Canada)

Author keywords

Arithmetic Coding; H.264, CABAC; VLSI

Indexed keywords

COMPUTATIONAL COMPLEXITY; FIELD PROGRAMMABLE GATE ARRAYS; IMAGE CODING; REDUCED INSTRUCTION SET COMPUTING;

ARITHMETIC CODING; ASIC SYNTHESIS; H.264, CABAC;

VLSI CIRCUITS;

EID: 32544458297     PISSN: 0277786X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1117/12.632676     Document Type: Conference Paper

References (10)

1. ITU, ITU-T Recommendation H.264: Advanced video coding for generic audiovisual services, May 2003.
2. D. Marpe, H. Schwarz, and T. Wiegend, "Context-based adaptive binary arithmetic coding in the H.264/AVC video compression standard," IEEE Transactions on Circuits and Systems for Video Technology 13, pp. 620-636, July 2003.
3. S. Sudharsanan and A. Cohen, "A hardware architecture for a context adaptive binary arithmetic coder," in Proc. of the SPIE, Embedded Processors for Multimedia & Communications II, pp. 104-112, Mar. 2005.
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8. H. Shojania and S. Sudharsanan, "A high performance CABAC encoder," in Proc. of the 3rd International IEEE Northeast Workshop on Circuits and Systems (NEWCAS'05), June 2005.
9. J. Mitchell and W. Pennebaker, JPEG: Still Image Data Compression Standard. Van Nostrand Reinhold. 1993.
10. ITU, H.264/AVC Reference Software, http://iphome.hhi.de/suehring/tml, ver. JM 8.2, July 2004.