Design and performance of a pixel-level pipelined-parallel architecture for high speed wavelet-based image compression

Computers and Electrical Engineering

Volumn 31, Issue 8, 2005, Pages 572-588

  Masoudnia, A ^a,d   Sarbazi Azad, H ^a,b,e   Boussakta, S ^c,e,f  

^a INSTITUTE FOR STUDIES IN THEORETICAL PHYSICS AND MATHEMATICS IPM   (Iran)

^b SHARIF UNIVERSITY OF TECHNOLOGY   (Iran)

^c UNIVERSITY OF LEEDS   (United Kingdom)

^d Sanjesh College of Computing and Statistics   (Iran)

^e Sharif University of Technology ^*

^f IEEE

Author keywords

Compression; Decompression; FPGA implementation; Image processing; Performance; Pipelining; Serial parallel architecture; Wavelet transform

Indexed keywords

HIGH SPEED PROCESSING; PIPELINING; SERIAL-PARALLEL ARCHITECTURE;

COMPUTER ARCHITECTURE; IMAGE COMPRESSION; IMAGE PROCESSING; SIGNAL PROCESSING; VLSI CIRCUITS; WAVELET TRANSFORMS;

PARALLEL PROCESSING SYSTEMS;

EID: 32444446861     PISSN: 00457906     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.compeleceng.2005.07.005     Document Type: Article

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