Three-dimensional logic architecture by four-terminal electrical switches (FES) beyond two-dimensional CMOS Architecture

2005 NSTI Nanotechnology Conference and Trade Show - NSTI Nanotech 2005 Technical Proceedings

Volumn , Issue , 2005, Pages 213-216

  Fujita, Shinobu ^a,b   Abe, Keiko ^a,b   Lee, Thomas H ^b  

^a TOSHIBA CORPORATION   (Japan)

^b Stanford University   (United States)

Author keywords

3D architecture; Carbon nanotube; Emerging memory; Post silicon technology; Switching device

Indexed keywords

CARBON NANOTUBES; CMOS INTEGRATED CIRCUITS; ELECTROLYTES; LOGIC GATES; NONVOLATILE STORAGE; SWITCHES;

3D ARCHITECTURE; CARBON NANOTUBE; POST-SILICON TECHNOLOGY; SWITCHING DEVICE;

COMPUTER ARCHITECTURE;

EID: 32044431912     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)

1. T. Sakamoto et al., Appl. Phys. Lett. Vol.82, 3032, 2003.
2. R. Symanczyk et al., Nonvolatile Memory Technology Symposium, 2004.
3. http://www.ovonyx.com/ovonyxtech.html
4. http://www.nantero.com/
5. K. Abe, S. Fujita and T. H. Lee, Technical digest of Nanotechnology and Trade Show 2005.